parallel interleaver Latest Research Papers

Research and Simulation on the MB Parallel Interleaver Cognitive Ultra Wideband System

Advances in Intelligent Systems and Computing - Intelligent Data Analysis and Applications ◽

10.1007/978-3-319-21206-7_39 ◽

2015 ◽

pp. 457-465 ◽

Cited By ~ 2

Author(s):

Bing Zhao ◽

Zhifang Wang ◽

Jiaqi Zhen

Keyword(s):

Ultra Wideband ◽

Parallel Interleaver

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S-Distance Based Deterministic Block Parallel Interleaver for Turbo Codes

Proceedings of the 2015 International Symposium on Computers and Informatics ◽

10.2991/isci-15.2015.285 ◽

2015 ◽

Author(s):

Yong Chen ◽

Lina Wang

Keyword(s):

Turbo Codes ◽

Parallel Interleaver

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Hardware Design of Parallel Interleaver Architectures: A Survey

Advanced Hardware Design for Error Correcting Codes ◽

10.1007/978-3-319-10569-7_9 ◽

2014 ◽

pp. 177-192 ◽

Cited By ~ 2

Author(s):

Cyrille Chavet ◽

Awais Hussain Sani ◽

Philippe Coussy

Keyword(s):

Hardware Design ◽

Parallel Interleaver

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Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2014.2309810 ◽

2014 ◽

Vol 61 (5) ◽

pp. 1376-1389 ◽

Cited By ~ 23

Author(s):

Guohui Wang ◽

Hao Shen ◽

Yang Sun ◽

Joseph R. Cavallaro ◽

Aida Vosoughi ◽

...

Keyword(s):

High Throughput ◽

Turbo Decoder ◽

Parallel Interleaver

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Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) ◽

10.1109/iscas.2013.6572102 ◽

2013 ◽

Cited By ~ 1

Author(s):

Guohui Wang ◽

Aida Vosoughi ◽

Hao Shen ◽

Joseph R. Cavallaro ◽

Yuanbin Guo

Keyword(s):

High Throughput ◽

Turbo Decoder ◽

Scheduling Scheme ◽

Parallel Interleaver

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A memory mapping approach for network and controller optimization in parallel interleaver architectures

Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI - GLSVLSI '13 ◽

10.1145/2483028.2483122 ◽

2013 ◽

Author(s):

Aroua Briki ◽

Cyrille Chavet ◽

Philippe Coussy

Keyword(s):

Mapping Approach ◽

Memory Mapping ◽

Parallel Interleaver

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A methodology based on Transportation problem modeling for designing parallel interleaver architectures

2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) ◽

10.1109/icassp.2011.5946806 ◽

2011 ◽

Cited By ~ 3

Author(s):

Awais Sani ◽

Philippe Coussy ◽

Cyrille Chavet ◽

Eric Martin

Keyword(s):

Transportation Problem ◽

Problem Modeling ◽

Parallel Interleaver

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Novel parallel interleaver based on Chinese Remainder Theorem

The 2nd International Conference on Information Science and Engineering ◽

10.1109/icise.2010.5690432 ◽

2010 ◽

Cited By ~ 1

Author(s):

Na Guo ◽

WenPing Ma ◽

Sheng Gao ◽

Tao Ruan

Keyword(s):

Chinese Remainder Theorem ◽

Parallel Interleaver

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A memory mapping approach for parallel interleaver design with multiples read and write accesses

Proceedings of 2010 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2010.5537955 ◽

2010 ◽

Cited By ~ 15

Author(s):

C. Chavet ◽

P. Coussy

Keyword(s):

Mapping Approach ◽

Memory Mapping ◽

Parallel Interleaver

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Towards radix-4, parallel interleaver design to support high-throughput turbo decoding for re-configurability

2010 IEEE Sarnoff Symposium ◽

10.1109/sarnof.2010.5469723 ◽

2010 ◽

Cited By ~ 4

Author(s):

Rizwan Asghar ◽

Dake Liu

Keyword(s):

High Throughput ◽

Turbo Decoding ◽

Parallel Interleaver

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parallel interleaver
Recently Published Documents

TOTAL DOCUMENTS

H-INDEX

Research and Simulation on the MB Parallel Interleaver Cognitive Ultra Wideband System

S-Distance Based Deterministic Block Parallel Interleaver for Turbo Codes

Hardware Design of Parallel Interleaver Architectures: A Survey

Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder

Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

A memory mapping approach for network and controller optimization in parallel interleaver architectures

A methodology based on Transportation problem modeling for designing parallel interleaver architectures

Novel parallel interleaver based on Chinese Remainder Theorem

A memory mapping approach for parallel interleaver design with multiples read and write accesses

Towards radix-4, parallel interleaver design to support high-throughput turbo decoding for re-configurability

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parallel interleaverRecently Published Documents

TOTAL DOCUMENTS

H-INDEX

Research and Simulation on the MB Parallel Interleaver Cognitive Ultra Wideband System

S-Distance Based Deterministic Block Parallel Interleaver for Turbo Codes

Hardware Design of Parallel Interleaver Architectures: A Survey

Parallel Interleaver Design for a High throughput HSPA+/LTE Multi-Standard Turbo Decoder

Parallel interleaver architecture with new scheduling scheme for high throughput configurable turbo decoder

A memory mapping approach for network and controller optimization in parallel interleaver architectures

A methodology based on Transportation problem modeling for designing parallel interleaver architectures

Novel parallel interleaver based on Chinese Remainder Theorem

A memory mapping approach for parallel interleaver design with multiples read and write accesses

Towards radix-4, parallel interleaver design to support high-throughput turbo decoding for re-configurability

parallel interleaver
Recently Published Documents