Product Design for Reuse of Waste Construction Wood——Teapot Tray Design Practices

By using waste construction wood as the main raw material, the design practice is based on increasing the storage function of the teapot tray. In the design of the product, we strive to show the unique texture of the waste construction wood. Structural design is based on tenon-and-mortise structure, convenient assembly and disassembly of products as design principles, easy replacement of parts and continuation of product life as design purpose, and teapot tray design through product modular design ideas. Modeling design combined with traditional cultural concepts to “turn waste into treasure.”

Design for Reuse in Business Process

When modeling a business process or when updating an existing one, a business analyzer is available to reuse business parts already operational. Indeed, to minimize time of creation and to reduce cost and complexity, a solution can be given by the reuse of some existing business parts. The need to reuse of some business parts to fulfill companies’ requirements leads to the need of extracting business fragments from the business process model. The aim of this paper is to propose a method which enables to obtain a business fragments from a business process. The main idea is to decompose a business process into small fragments. These fragments have the ability to be reused for building a new business process or updating an existing one. The method the authors propose is presented as guidelines that allow the decomposition of business process to enable having a reusable business fragments, their method is based on variability in business process modeled in BPMN. The method also takes into account the business goal of each extracted fragment. The proposed method is presented as a process along with a meta-model to facilitate the understanding of the concepts related to BPMN. An algorithm that illustrates their method is also presented in order to use it for a further implementation. The paper also includes users’ experiments to validate our method.

A Study of Reusing Smartphones to Augment Elementary School Education

Society faces a severe environmental challenge posed by the rapid advance of technology scaling. The high cost in manufacturing energy, materials, and disposal is worrisome with the increasing number of smartphones. To mitigate the impact of future devices, the authors propose a design for reuse model in which obsolete devices will be reused for a class of applications that can be satisfied with older, less reliable technology. In particular, the authors find a good match between the reuse of smartphones and educational applications. The experiments indicate that the resource requirements of educational applications can be satisfied by repurposed smartphones. The key challenge is the design of software that can adapt to extreme heterogeneity of devices. To this end, the authors explore smartphone evolutions and characterize different types of heterogeneities among different generations of smartphones. The authors propose insights to aid establishing a sustainable model of designing mobile applications for phone reuse.

High Level Design Approach for FPGA Implementation of ANNs

Artificial neural networks (ANNs) are systems which are derived from the field of neuroscience and are characterized by intensive arithmetic operations. These networks display interesting features such as parallelism, classification, optimization, adaptation, generalization and associative memories. Since the McCulloch and Pitts pioneering work (McCulloch, W.S., & Pitts, W. (1943), there has been much discussion on the topic of ANNs implementation, and a huge diversity of ANNs has been designed (C. Lindsey & T. Lindblad, 1994). The benefits of using such implementations is well discussed in a paper by R. Lippmann (Richard P. Lipmann, 1984): “The great interest of building neural networks remains in the high speed processing that can be achieved through massively parallel implementation”. In another paper Clark S. Lindsey (C.S Lindsey, Th. Lindbald, 1995) posed a real dilemma of hardware implementation: “Built a general, but probably expensive system that can be reprogrammed for several kinds of tasks like CNAPS for example? Or build a specialized chip to do one thing but very quickly, like the IBM ZISC Processor”. To overcome this dilemma, most researchers agree that an ideal solution should relay the performances obtained using specific hardware implementation and the flexibility allowed by software tools and general purpose chips. Since their commercial introduction in the mid- 1980’s, and due to the advances in the development of both of the microelectronic technology and the specific CAD tools, FPGAs devices have progressed in an evolutionary and revolutionary way. The evolution process has allowed faster and bigger FPGAs, better CAD tools and better technical support. The revolution process concerns the introduction of high performances multipliers, Microprocessors and DSP functions. This has a direct incidence to FPGA implementation of ANNs and a lot of research has been carried to investigate the use of FPGAs in ANNs implementation (Amos R. Omandi & Jagath C. rajapakse, 2006). Another attractive key feature of FPGAs is their flexibility, which can be obtained at different levels: exploitation of the programmability of FPGA, dynamic reconfiguration or run time reconfiguration (RTR), (Xilinx XAPP290, 2004) and the application of the design for reuse concept (Keating, Michael; Bricaud, Pierre, 2002). However, a big disadvantage of FPGAs is the low level hardware oriented programming model needed to fully exploit the FPGA’s potential performances. High level based VHDL synthesis tools have been proposed to bridge the gap between the high level application requirements and the low level FPGA hardware but these tools are not algorithmic or application specific. Thus, special concepts need to be developed for automatic ANN implementation before using synthesis tools. In this paper, we present a high level design methodology for ANN implementation that attempts to build a bridge between the synthesis tool and the ANN design requirements. This method offers a high flexibility in the design while achieving speed/area performances constraints. The three implementation figures of the ANN based back propagation algorithm are considered. These are the off-type implementation, the on-chip global implementation and the dynamic reconfiguration choices of the ANN. To achieve our goal, a design for reuse strategy has been applied. To validate our approach, three case studies are considered using the Virtex-II and Virtex-4 FPGA devices. A comparative study is done and new conclusions are given.