A batch scheduling model for a three-stage flow shop with job and batch processors considering a sampling inspection to minimize expected total actual flow time

Purpose: This research develops a batch scheduling model for a three-stage flow shop with job processors in the first and second stages and a batch processor in the third stage. The model integrates production process activities and a product inspection activity to minimize the expected total actual flow time.Design/methodology/approach: The problem of batch scheduling for a three-stage flow shop is formulated as a mathematical model, and a heuristic algorithm is proposed to solve the problem. This model applies backward scheduling to accommodate the objective of minimizing the expected total actual flow time.Findings: This research has proposed a batch scheduling model for a three-stage flow shop with job and batch processors to produce multiple items and an algorithm to solve the model. The objective is to minimize total actual time. The resulting production batches can be sequenced between all types of products to minimize idle time, and the batch processor capacity affects the sample size and indirectly affects the production batch size.Originality/value: This research develops a batch scheduling model for a three-stage flow shop constituting job and batch processors and carrying out integrated production and inspection activities to minimize the expected total actual flow time

Simulation-Based Analysis on Operational Control of Batch Processors in Wafer Fabrication

In semiconductor wafer fabrication (wafer fab), wafers go through hundreds of process steps on a variety of processing machines for electrical circuit building operations. One of the special features in the wafer fabs is that there exist batch processors (BPs) where several wafer lots are processed at the same time as a batch. The batch processors have a significant influence on system performance because the repetitive batching and de-batching activities in a reentrant product flow system lead to non-smooth product flows with high variability. Existing research on the BP control problems has mostly focused on the local performance, such as waiting time at the BP stations. This paper attempts to examine how much BP control policies affect the system-wide behavior of the wafer fabs. A simulation model is constructed with which experiments are performed to analyze the performance of BP control rules under various production environments. Some meaningful insights on BP control decisions are identified through simulation results.

QoS Oriented Enhancement based on the Analysis of Dynamic Job Scheduling in HPC

With the advent of High Performance Computing (HPC) in the large-scale parallel computational environment, better job scheduling and resource allocation techniques are required to deliver Quality of Service (QoS). Therefore, job scheduling on a large-scale parallel system has been studied to minimize the queue time, response time, and to maximize the overall system utilization. The objective of this paper is to touch upon the recent methods used for dynamic resource allocation across multiple computing nodes and the impact of scheduling algorithms. In addition, a quantitative approach which explains a trend line analysis on dynamic allocation for batch processors is depicted. Throughout the survey, the trends in research on dynamic allocation and parallel computing is identified, besides, highlights the potential areas for future research and development. This study proposes the design for an efficient dynamic scheduling algorithm based on the Quality-of-Service. The analysis provides a compelling research platform to optimize dynamic scheduling of jobs in HPC.