Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs

2014 ◽  
Author(s):  
Kitae Park ◽  
Geunho Kim ◽  
Taewhan Kim
Keyword(s):  
Clock Tree ◽  
Buffer Sizing ◽  
Clock Tree Synthesis ◽  
Power Mode ◽  
Multiple Power ◽  
Tree Synthesis

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits

2011 ◽  
Vol E94-C (3) ◽  
pp. 288-295 ◽  
Author(s):  
Kazuyoshi TAKAGI ◽  
Yuki ITO ◽  
Shota TAKESHIMA ◽  
Masamitsu TANAKA ◽  
Naofumi TAKAGI
Keyword(s):  
Clock Tree ◽  
Clock Tree Synthesis ◽  
Tree Synthesis

scholarly journals Reducing the Delay by Optimizing the Via in Compact Automatic Metal Routing Algorithm

2019 ◽  
Vol 8 (10) ◽  
pp. 4512-4515
Keyword(s):  
Routing Algorithm ◽  
Deep Submicron ◽  
Clock Tree ◽  
Channel Routing ◽  
Ir Drop ◽  
Clock Tree Synthesis ◽  
Tree Synthesis ◽  
Metal Layers ◽  
Synthesis Stage

The Very Deep Submicron Technology (VDSM) shrinking rapidly, we have 22nm, 14nm, 7nm and now research going on 5nm technology. That means size of the transistor shrinking, and number of interconnections increased as well. Resulting interconnections playing a major role in delay, IR drop, area etc. To reduce the delay, we are utilizing higher metal layers. Further we gone for Compact Automatic Metal Routing, nothing but Over the cell channel routing to efficiently perform routing, but the problem for such type of routing technique, stacked vias needed and that results increased resistance, delay, IR drop will degrade the performance. That may be obstacle to meet timing in Clock Tree Synthesis stage (CTS). This paper mainly focus on reducing the delay further by designing the via structure by using the tool cadence encounter

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