A Hybrid Packet/Circuit-switched Router to Accelerate Memory Access in NoC-based Chip Multiprocessors

2015 ◽  
Author(s):  
Abbas Mazloumi ◽  
Mehdi Modarressi
Keyword(s):  
Chip Multiprocessors ◽  
Memory Access

scholarly journals Run-time thermal management based on task migration techniques in 3D chip multiprocessors

2021 ◽  
Author(s):  
Sulaiman Obaid Aljeddani
Keyword(s):  
Thermal Management ◽  
Chip Multiprocessors ◽  
Core Layer ◽  
Memory Access ◽  
Experimental Results ◽  
Peak Temperature ◽  
Task Migration ◽  
The Core ◽  
Time Task ◽  
Run Time

The industry trend of Chip Multiprocessors (CMPs) architecture is to move from 2D CMPs to 3D CMPs architecture for obtain higher performance, more reliability, and reduced memory access latency. However, one key challenge in designing the 3D CMPs is the thermal issue as a result of maximizing the throughput . Therefore, applying Runtime Thermal Management (RTM) has become crucial for controlling thermal hotspots. In this thesis, two methods of run-time task migration are presented to balance the temperature and reduce the number of hotspots in 3D CMPs. The proposed techniques consider hotspots both in the core and the memory layers simultaneously to make the optimum run-time task migration decisions. The first proposed approach is divided into two algorithms working in parallel, which aim at maximizing the throughput on the 3D CMPs while satisfying the peak temperature constraints. Experimental results show that the proposed architecture yields up to 60% reduction in overall chip energy. The proposed architecture improves the IPC for canneal and fluidanimate applications by 18% and 14%, respectively. In the second method, the proposed technique migrates the hottest core with the optimal coldest core instead of the coldest core in the core layer. The optimal coldest core is selected by considering hotspots.

Reducing memory access latency with asymmetric DRAM bank organizations

2013 ◽  
Vol 41 (3) ◽  
pp. 380-391 ◽  
Author(s):  
Young Hoon Son ◽  
O. Seongil ◽  
Yuhwan Ro ◽  
Jae W. Lee ◽  
Jung Ho Ahn
Keyword(s):  
Memory Access ◽  
Access Latency

scholarly journals On the Applicability of PEBS based Online Memory Access Tracking for Heterogeneous Memory Management at Scale

2018 ◽  
Author(s):  
Aleix Roca Nonell ◽  
Balazs Gerofi ◽  
Leonardo Bautista-Gomez ◽  
Dominique Martinet ◽  
Vicenç Beltran Querol ◽  
...  
Keyword(s):  
Memory Management ◽  
Memory Access

scholarly journals Pre-Emphasis Pulse Design for Random-Access Memory

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1454
Author(s):  
Yoshihiro Sugiura ◽  
Toru Tanzawa
Keyword(s):  
Time Constant ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Memory Access ◽  
Access Time ◽  
Access Memory ◽  
Delay Times ◽  
Cell Current ◽  
The Impact

This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time.

Fast synchronization for chip multiprocessors

2005 ◽  
Vol 33 (4) ◽  
pp. 64-69 ◽  
Author(s):  
Jack Sampson ◽  
Rubén González ◽  
Jean-Francois Collard ◽  
Norman P. Jouppi ◽  
Mike Schlansker
Keyword(s):  
Chip Multiprocessors
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