Automatic Circuit Sizing Technique for the Analog Circuits with Flexible TFTs Considering Process Variation and Bending Effects

2013 ◽  
Author(s):  
Yen-Lung Chen ◽  
Wan-Rong Wu ◽  
Guan-Ruei Lu ◽  
Chien-Nan Jimmy Liu
Keyword(s):  
Analog Circuits ◽  
Process Variation ◽  
Circuit Sizing

scholarly journals Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation

2013 ◽  
Vol 21 (10) ◽  
pp. 1811-1822 ◽  
Author(s):  
Rajeev Narayanan ◽  
Ibtissem Seghaier ◽  
Mohamed H. Zaki ◽  
Sofiene Tahar
Keyword(s):  
Analog Circuits ◽  
Process Variation ◽  
Run Time

A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier

2012 ◽  
Vol 47 (1) ◽  
pp. 301-309 ◽  
Author(s):  
Koichi Ishida ◽  
Tsung-Ching Huang ◽  
Kentaro Honda ◽  
Tsuyoshi Sekitani ◽  
Hiroyoshi Nakajima ◽  
...  
Keyword(s):  
Analog Circuits ◽  
Process Variation ◽  
Floating Gate ◽  
Energy Meter

A case study of process-variation effect to SoC analog circuits

2011 ◽  
Author(s):  
Mohd Azman Abdul Latif ◽  
Noohul Basheer Zain Ali ◽  
Fawnizu Azmadi Hussin
Keyword(s):  
Analog Circuits ◽  
Process Variation

A Unified Analog Synthesis Approach Considering Parasitic Effects and Process Variations

2015 ◽  
pp. 55-70
Author(s):  
Yen-Lung Chen ◽  
Chien-Nan Jimmy Liu
Keyword(s):  
Analog Circuits ◽  
Process Variations ◽  
Experimental Results ◽  
Unified Approach ◽  
Circuit Performance ◽  
Circuit Sizing ◽  
Analog Synthesis ◽  
Hardware Overhead ◽  
Parasitic Effects ◽  
Synthesis Approach

Manually designing the analog/RF and power circuits to meet requirements is often considered a difficult task that takes a lot of time. Several automatic circuit-sizing approaches have been proposed for typical analog circuits to solve this bottleneck, but the performance and yield is unexpected if the non-ideal effects are not considered. In this chapter, an equation-based automatic synthesis approach for analog circuits is proposed. The layout-induced parasitic effects and process variations are also considered simultaneously to guarantee the circuit performance after manufacturing. As shown in the experimental results, the proposed approach successfully solves the unreachable specification in previous work and keeps the performance and yield of the generated circuit even in post-layout simulations. The incurred hardware overhead is also reduced by using the proposed unified approach, which demonstrates the feasibility and efficiency of this approach.

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