scholarly journals Stack-through silicon via dynamic power consumption optimization in three-dimensional integrated circuit

2015 ◽  
Vol 64 (2) ◽  
pp. 026601
Author(s):  
Dong Gang ◽  
Wu Wen-Shan ◽  
Yang Yin-Tang
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Three Dimensional ◽  
Through Silicon Via ◽  
Dynamic Power ◽  
Power Consumption Optimization ◽  
Three Dimensional Integrated Circuit

Enhancement of through Silicon via Sidewall Quality by Nanosecond Laser Pulses with Chemical Etching Process

2012 ◽  
Vol 579 ◽  
pp. 3-9 ◽  
Author(s):  
Chao Wei Tang ◽  
Shih Chieh Tseng ◽  
Hong Tsu Young ◽  
Kuan Ming Li ◽  
Mike Yang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Chemical Etching ◽  
Three Dimensional ◽  
Laser Pulses ◽  
Nanosecond Laser ◽  
Wafer Level ◽  
Sidewall Roughness ◽  
Through Silicon Via ◽  
Three Dimensional Integrated Circuit ◽  
Micrometer Scale

Through-silicon via (TSV) is an emerging technology for three-dimensional integrated circuit, system in package, and wafer level packaging applications. In this study, a wet chemical etching (WCE) process has been employed to enhance the sidewall quality of TSVs fabricated using nanosecond (ns) laser pulses. Experimental results show that the TSV sidewall roughness can be markedly reduced, from micrometer scale to nanometer scale. We concluded that the proposed method would enable semiconductor manufactures to use ns laser drilling for industrial TSV fabrication as the desired TSV sidewall quality can be achieved by incorporating the WCE process, which is suitable for mass production.

Macroinspection methodology for through silicon via array in three-dimensional integrated circuit

2014 ◽  
Vol 13 (1) ◽  
pp. 011204 ◽  
Author(s):  
Yoshihiko Fujimori ◽  
Takashi Tsuto ◽  
Hiroyuki Tsukamoto ◽  
Kazuya Okamoto ◽  
Kyoichi Suwa
Keyword(s):  
Integrated Circuit ◽  
Three Dimensional ◽  
Through Silicon Via ◽  
Three Dimensional Integrated Circuit
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