scholarly journals One-shadow-mask ultralow-voltage indium-tin-oxide thin-film transistors on paper substrates

2012 ◽  
Vol 61 (4) ◽  
pp. 047202
Author(s):  
Mao Yan-Kai ◽  
Jiang Jie ◽  
Zhou Bin ◽  
Dou Wei
Keyword(s):  
Thin Film ◽  
Tin Oxide ◽  
Indium Tin Oxide ◽  
Thin Film Transistors ◽  
Oxide Thin Film ◽  
Shadow Mask ◽  
Paper Substrates

In-plane-gate indium-tin-oxide thin-film transistors self-assembled on paper substrates

2011 ◽  
Vol 98 (11) ◽  
pp. 113507 ◽  
Author(s):  
Jie Jiang ◽  
Jia Sun ◽  
Wei Dou ◽  
Bin Zhou ◽  
Qing Wan
Keyword(s):  
Thin Film ◽  
Tin Oxide ◽  
Indium Tin Oxide ◽  
Thin Film Transistors ◽  
Oxide Thin Film ◽  
Self Assembled ◽  
Paper Substrates

Amorphous Indium Tin Oxide Thin-Film Transistors Fabricated by Cosputtering Technique

2016 ◽  
Vol 63 (3) ◽  
pp. 1072-1077 ◽  
Author(s):  
Xin Xu ◽  
Letao Zhang ◽  
Yang Shao ◽  
Zheyuan Chen ◽  
Yong Le ◽  
...  
Keyword(s):  
Thin Film ◽  
Tin Oxide ◽  
Indium Tin Oxide ◽  
Thin Film Transistors ◽  
Oxide Thin Film

Solution-processed zinc-indium-tin oxide thin-film transistors for flat-panel displays

2013 ◽  
Vol 103 (7) ◽  
pp. 072110 ◽  
Author(s):  
Bo Sung Kim ◽  
Yeon Taek Jeong ◽  
Doohyoung Lee ◽  
TaeYoung Choi ◽  
Seung-Ho Jung ◽  
...  
Keyword(s):  
Thin Film ◽  
Tin Oxide ◽  
Indium Tin Oxide ◽  
Thin Film Transistors ◽  
Oxide Thin Film ◽  
Flat Panel Displays ◽  
Flat Panel ◽  
Solution Processed ◽  
Zinc Indium Tin Oxide

scholarly journals Low-voltage self-assembled indium tin oxide thin-film transistors gated by microporous SiO2 treated by H3PO4

RSC Advances ◽  
2019 ◽  
Vol 9 (53) ◽  
pp. 30715-30719 ◽  
Author(s):  
Wei Dou ◽  
Yuanyuan Tan
Keyword(s):  
Thin Film ◽  
Tin Oxide ◽  
Indium Tin Oxide ◽  
Electric Double Layer ◽  
Thin Film Transistors ◽  
Room Temperature ◽  
Gate Dielectric ◽  
Low Voltage ◽  
Oxide Thin Film ◽  
Self Assembled

Ultralow-voltage (0.8 V) thin-film transistors (TFTs) using self-assembled indium-tin-oxide (ITO) as the semiconducting layer and microporous SiO2 immersed in 5% H3PO4 for 30 minutes with huge electric-double-layer (EDL) capacitance as the gate dielectric are fabricated at room temperature.

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