scholarly journals Development of Compute-in-Memory Memristive Crossbar Architecture with Composite Memory Cells

2021 ◽  
Author(s):  
Mehri Teimoory ◽  
Amirali Amirsoleimani ◽  
Arash Ahmadi ◽  
Majid Ahmadi
Keyword(s):  
Energy Efficiency ◽  
Memory Cell ◽  
Von Neumann ◽  
Crossbar Array ◽  
Computing Platforms ◽  
Crossbar Architecture ◽  
Processing And Storage ◽  
Memristor Crossbar ◽  
Logic Functions ◽  
Array Performance

In this chapter, we discuss the compute-in-memory memristive architectures and develop a 2M1M crossbar array which can be applied for both memory and logic applications. In the first section of this chapter, we briefly discuss compute-in-memory memristive architectural concepts and specifically investigate the current state off the art composite memristor-based switch cells. Also, we define their applications e.g. digital/analog logic, memory, etc. along with their drawbacks and implementation limitations. These composite cells can be designed to be adapted into different design needs can enhance the performance of the memristor crossbar array while preserving their advantages in terms of area and/or energy efficiency. In the second section of the chapter, we discuss a 2M1M memristor switch and its functionality which can be applied into memory crossbars and enables both memory and logic functions. In the next section of the chapter, we define logic implementation by using 2M1M cells and describe variety of in-memory digital logic 2M1M gates. In the next section of the chapter, 2M1M crossbar array performance to be utilized as memory platform is described and we conceived pure memristive 2M1M crossbar array maintains high density, energy efficiency and low read and write time in comparison with other state of art memory architectures. This chapter concluded that utilizing a composite memory cell based on non-volatile memristor devices allow a more efficient combination of processing and storage architectures (compute-in-memory) to overcome the memory wall problem and enhance the computational efficiency for beyond Von-Neumann computing platforms.

scholarly journals Towards Neuromorphic Learning Machines Using Emerging Memory Devices with Brain-Like Energy Efficiency

2018 ◽  
Vol 8 (4) ◽  
pp. 34 ◽  
Author(s):  
Vishal Saxena ◽  
Xinyu Wu ◽  
Ira Srivastava ◽  
Kehan Zhu
Keyword(s):  
Machine Learning ◽  
Energy Efficiency ◽  
Deep Learning ◽  
Large Scale ◽  
Learning Algorithms ◽  
Memory Devices ◽  
Cognitive Computing ◽  
Mixed Signal ◽  
Von Neumann ◽  
Emerging Memory

The ongoing revolution in Deep Learning is redefining the nature of computing that is driven by the increasing amount of pattern classification and cognitive tasks. Specialized digital hardware for deep learning still holds its predominance due to the flexibility offered by the software implementation and maturity of algorithms. However, it is being increasingly desired that cognitive computing occurs at the edge, i.e., on hand-held devices that are energy constrained, which is energy prohibitive when employing digital von Neumann architectures. Recent explorations in digital neuromorphic hardware have shown promise, but offer low neurosynaptic density needed for scaling to applications such as intelligent cognitive assistants (ICA). Large-scale integration of nanoscale emerging memory devices with Complementary Metal Oxide Semiconductor (CMOS) mixed-signal integrated circuits can herald a new generation of Neuromorphic computers that will transcend the von Neumann bottleneck for cognitive computing tasks. Such hybrid Neuromorphic System-on-a-chip (NeuSoC) architectures promise machine learning capability at chip-scale form factor, and several orders of magnitude improvement in energy efficiency. Practical demonstration of such architectures has been limited as performance of emerging memory devices falls short of the expected behavior from the idealized memristor-based analog synapses, or weights, and novel machine learning algorithms are needed to take advantage of the device behavior. In this article, we review the challenges involved and present a pathway to realize large-scale mixed-signal NeuSoCs, from device arrays and circuits to spike-based deep learning algorithms with ‘brain-like’ energy-efficiency.

Wafer‐Scale 2D Hafnium Diselenide Based Memristor Crossbar Array for Energy‐Efficient Neural Network Hardware

2021 ◽  
pp. 2103376 ◽  
Author(s):  
Sifan Li ◽  
Mei‐Er Pam ◽  
Yesheng Li ◽  
Li Chen ◽  
Yu‐Chieh Chien ◽  
...  
Keyword(s):  
Neural Network ◽  
Energy Efficient ◽  
Wafer Scale ◽  
Crossbar Array ◽  
Neural Network Hardware ◽  
Memristor Crossbar

Reconfigurable nonvolatile boolean logic with one-transistor-two-memristor for in-memory computing

2021 ◽  
Author(s):  
Ziling Wang ◽  
Li Luo ◽  
Jie Li ◽  
Lidan Wang ◽  
shukai duan
Keyword(s):  
Large Scale ◽  
Full Adder ◽  
Boolean Logic ◽  
Device Structure ◽  
Von Neumann ◽  
Computing Paradigm ◽  
Operation Process ◽  
Strong Candidate ◽  
High Flexibility ◽  
Logic Functions

Abstract In-memory computing is highly expected to break the von Neumann bottleneck and memory wall. Memristor with inherent nonvolatile property is considered to be a strong candidate to execute this new computing paradigm. In this work, we have presented a reconfigurable nonvolatile logic method based on one-transistor-two-memristor (1T2M) device structure, inhibiting the sneak path in the large-scale crossbar array. By merely adjusting the applied voltage signals, all 16 binary Boolean logic functions can be achieved in a single cell. More complex computing tasks including one-bit parallel full adder and Set-Reset latch have also been realized with optimization, showing simple operation process, high flexibility, and low computational complexity. The circuit verification based on cadence PSpice simulation is also provided, proving the feasibility of the proposed design. The work in this paper is intended to make progress in constructing architectures for in-memory computing paradigm.

scholarly journals Plasmonic nanogap enhanced phase-change devices with dual electrical-optical functionality

2019 ◽  
Vol 5 (11) ◽  
pp. eaaw2687 ◽  
Author(s):  
Nikolaos Farmakidis ◽  
Nathan Youngblood ◽  
Xuan Li ◽  
James Tan ◽  
Jacob L. Swett ◽  
...  
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Memory Cell ◽  
Communications Technologies ◽  
New Strategy ◽  
On Chip ◽  
Processing And Storage ◽  
Electrical Signaling ◽  
And Storage ◽  
Change Memory

Modern-day computers rely on electrical signaling for the processing and storage of data, which is bandwidth-limited and power hungry. This fact has long been realized in the communications field, where optical signaling is the norm. However, exploiting optical signaling in computing will require new on-chip devices that work seamlessly in both electrical and optical domains, without the need for repeated electrical-to-optical conversion. Phase-change devices can, in principle, provide such dual electrical-optical operation, but assimilating both functionalities into a single device has so far proved elusive owing to conflicting requirements of size-limited electrical switching and diffraction-limited optical response. Here, we combine plasmonics, photonics, and electronics to deliver an integrated phase-change memory cell that can be electrically or optically switched between binary or multilevel states. Crucially, this device can also be simultaneously read out both optically and electrically, offering a new strategy for merging computing and communications technologies.

A memristor crossbar array of titanium oxide for non-volatile memory and neuromorphic applications

2017 ◽  
Vol 32 (6) ◽  
pp. 065014 ◽  
Author(s):  
Haider Abbas ◽  
Yawar Abbas ◽  
Son Ngoc Truong ◽  
Kyeong-Sik Min ◽  
Mi Ra Park ◽  
...  
Keyword(s):  
Titanium Oxide ◽  
Crossbar Array ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Memristor Crossbar
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