scholarly journals Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

10.5772/67257 ◽  
2017 ◽  
Author(s):  
Ajay Kumar Singh
Keyword(s):  
Power Efficient ◽  
Fpga Architecture ◽  
Sram Cell ◽  
Efficient Data

A power-efficient impoved-stability 6T SRAM cell in 45nm Multi-Channel FET technology

2008 ◽  
Author(s):  
Olivier Thomas ◽  
Bernard Guillaumot ◽  
Thomas Ernst ◽  
Bastien Cousin ◽  
Olivier Rozeau
Keyword(s):  
Power Efficient ◽  
Sram Cell

scholarly journals A New ALU Design using PNS-FCR: Static CMOS Logic for Microprocessors

2019 ◽  
Vol 8 (6S2) ◽  
pp. 876-882
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Design Methodology ◽  
Total Power ◽  
Data Path ◽  
Power Efficient ◽  
Efficient Data ◽  
Main Component ◽  
Static Logic ◽  
Important Design

Arithmetic Logic Unit (ALU) is the main component in the processors. Most important design consideration in integrated circuit is power. In all the components of ALU data path is the active one and it consumes more percent of power in the total power. In the modern microprocessors it is important to have power efficient data paths. To reduce the power consumption in microprocessors the ALU is designed using PNS-FCR static CMOS logic. In this paper static CMOS logic is used to reduce power consumption. Static technique does not need any clock. So it leads to less power consumption. For the implementation of the ALU with the PNS-FCR static logic mentor graphics tool is used. The power consumption of ALU is compared with and without using FCR. An 8-bit ALU is designed in mentor graphics with 130nm technology. The proposed design methodology gives less power consumption

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