Design Trade‐Offs for FPGA Implementation of LDPC Decoders

E09: An FPGA implementation of Rijndael: Trade-offs for side-channel security

IFAC Proceedings Volumes ◽

10.1016/s1474-6670(17)30651-1 ◽

2004 ◽

Vol 37 (20) ◽

pp. 493-498 ◽

Cited By ~ 2

Author(s):

Nele Mentens ◽

Lejla Batina ◽

Bart Preneel ◽

Ingrid Verbauwhede

Keyword(s):

Fpga Implementation ◽

Side Channel ◽

Trade Offs

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Investigation of area and speed trade-offs in FPGA implementation of an image correlation algorithm

2012 13th International Workshop on Cellular Nanoscale Networks and their Applications ◽

10.1109/cnna.2012.6331455 ◽

2012 ◽

Cited By ~ 1

Author(s):

Z. Kincses ◽

Zs. Voroshazi ◽

Z. Nagy ◽

P. Szolgay ◽

T. Laviniu ◽

...

Keyword(s):

Fpga Implementation ◽

Image Correlation ◽

Correlation Algorithm ◽

Trade Offs

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Desarrollo de encriptado AES en FPGA

10.35537/10915/4101 ◽

2006 ◽

Author(s):

◽

Mónica Cristina Liberatori

Keyword(s):

Fpga Implementation ◽

Advanced Encryption Standard ◽

Trade Offs ◽

Logic Cells ◽

Test Vectors ◽

Vhdl Code

The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen and recently selected as the official Advanced Encryption Standard (AES) is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This thesis presents an 8-bit FPGA implementation of the 128-bit block and 128 bit-key AES cipher. Selected FPGA Family is Altera Flex 10K. The cipher operates at 25 MHz and consumes 470 clock cycles for algorithm encryption, resulting in a throughput of 6.8 Mbps. Synthesis results in the use of 460 logic cells and 4480 memory bits. The VHDL code was simulated using the test vectors provided in the AES submission package. The results are functionally correct. The architecture needs fewer logic cells than other ciphers and uses as few memory blocks as possible. The design goals were area and cost optimisation.

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Novel players fine-tune plant trade-offs

Essays in Biochemistry ◽

10.1042/bse0580083 ◽

2015 ◽

Vol 58 ◽

pp. 83-100 ◽

Cited By ~ 25

Author(s):

Selena Gimenez-Ibanez ◽

Marta Boter ◽

Roberto Solano

Keyword(s):

Ubiquitin Ligase ◽

Feedback Loop ◽

Molecular Level ◽

26S Proteasome ◽

Signalling Molecules ◽

Transcriptional Reprogramming ◽

Trade Offs ◽

Jaz Proteins ◽

Regulatory Feedback Loop ◽

Fine Tune

Jasmonates (JAs) are essential signalling molecules that co-ordinate the plant response to biotic and abiotic challenges, as well as co-ordinating several developmental processes. Huge progress has been made over the last decade in understanding the components and mechanisms that govern JA perception and signalling. The bioactive form of the hormone, (+)-7-iso-jasmonyl-l-isoleucine (JA-Ile), is perceived by the COI1–JAZ co-receptor complex. JASMONATE ZIM DOMAIN (JAZ) proteins also act as direct repressors of transcriptional activators such as MYC2. In the emerging picture of JA-Ile perception and signalling, COI1 operates as an E3 ubiquitin ligase that upon binding of JA-Ile targets JAZ repressors for degradation by the 26S proteasome, thereby derepressing transcription factors such as MYC2, which in turn activate JA-Ile-dependent transcriptional reprogramming. It is noteworthy that MYCs and different spliced variants of the JAZ proteins are involved in a negative regulatory feedback loop, which suggests a model that rapidly turns the transcriptional JA-Ile responses on and off and thereby avoids a detrimental overactivation of the pathway. This chapter highlights the most recent advances in our understanding of JA-Ile signalling, focusing on the latest repertoire of new targets of JAZ proteins to control different sets of JA-Ile-mediated responses, novel mechanisms of negative regulation of JA-Ile signalling, and hormonal cross-talk at the molecular level that ultimately determines plant adaptability and survival.

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Dual Goals for Speed and Accuracy on the Same Performance Task

Journal of Personnel Psychology ◽

10.1027/1866-5888/a000063 ◽

2012 ◽

Vol 11 (3) ◽

pp. 118-126 ◽

Cited By ~ 3

Author(s):

Olive Emil Wetter ◽

Jürgen Wegge ◽

Klaus Jonas ◽

Klaus-Helmut Schmidt

Keyword(s):

Memory Scanning ◽

Performance Task ◽

Performance Tasks ◽

Trade Off ◽

Test Experiment ◽

Trade Offs ◽

New Finding ◽

Sternberg Paradigm ◽

Speed Accuracy ◽

Speed And Accuracy

In most work contexts, several performance goals coexist, and conflicts between them and trade-offs can occur. Our paper is the first to contrast a dual goal for speed and accuracy with a single goal for speed on the same task. The Sternberg paradigm (Experiment 1, n = 57) and the d2 test (Experiment 2, n = 19) were used as performance tasks. Speed measures and errors revealed in both experiments that dual as well as single goals increase performance by enhancing memory scanning. However, the single speed goal triggered a speed-accuracy trade-off, favoring speed over accuracy, whereas this was not the case with the dual goal. In difficult trials, dual goals slowed down scanning processes again so that errors could be prevented. This new finding is particularly relevant for security domains, where both aspects have to be managed simultaneously.

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