scholarly journals Adaptive Control Methodology for High-performance Low-power VLSI Design

10.5772/6437 ◽  
2009 ◽  
Author(s):  
Se-Joong Lee
Keyword(s):  
Adaptive Control ◽  
Low Power ◽  
High Performance ◽  
Vlsi Design ◽  
Low Power Vlsi Design ◽  
Control Methodology

Low-Power VLSI Design: An Overview

1995 ◽  
pp. 1-12
Author(s):  
Abdellatif Bellaouar ◽  
Mohamed I. Elmasry
Keyword(s):  
Low Power ◽  
Vlsi Design ◽  
Low Power Vlsi Design

scholarly journals A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

2013 ◽  
pp. 78-82
Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Vlsi Design ◽  
Flip Flop ◽  
Ring Counter ◽  
Double Edge ◽  
Low Power Cmos ◽  
Cmos Vlsi

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

scholarly journals A Glitch-Free Novel DET-FF in 22 nm CMOS for Low-Power Application

2018 ◽  
Vol 2018 ◽  
pp. 1-6 ◽  
Author(s):  
Sumitra Singar ◽  
N. K. Joshi ◽  
P. K. Ghosh
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Performance ◽  
Vlsi Design ◽  
Total System ◽  
Clock Frequency ◽  
Flip Flop ◽  
Digital Vlsi ◽  
Feedback Structure ◽  
Power Application

Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET) techniques. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In the proposed design, we have used an internal dual feedback structure. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system.

Low-power VLSI design of arithmetic and logic circuits using the multiple-threshold CMOS technique

2021 ◽  
pp. 624-632
Author(s):  
Prachi Kataria ◽  
Anuwarti Rai ◽  
Aanchal Singh ◽  
Ashwin Anand ◽  
Raman Kapoor ◽  
...  
Keyword(s):  
Low Power ◽  
Vlsi Design ◽  
Logic Circuits ◽  
Multiple Threshold ◽  
Low Power Vlsi Design
Sign in / Sign up

Export Citation Format

Share Document