scholarly journals Study on Low-Power Image Processing for Gastrointestinal Endoscopy

VLSI Design ◽  
10.5772/33771 ◽  
2012 ◽  
Author(s):  
Meng-Chun Lin
Keyword(s):  
Image Processing ◽  
Low Power ◽  
Gastrointestinal Endoscopy

scholarly journals FLIP-Q: A QCIF Resolution Focal-Plane Array for Low-Power Image Processing

2012 ◽  
pp. 67-109 ◽  
Author(s):  
Jorge Fernández-Berni ◽  
Ricardo Carmona-Galán ◽  
Ángel Rodríguez-Vázquez
Keyword(s):  
Image Processing ◽  
Low Power ◽  
Focal Plane ◽  
Focal Plane Array

Efficient Low-Power Compact Hardware Units for Real-Time Image Processing

2014 ◽  
Vol 9 (4) ◽  
pp. 24-39
Author(s):  
Khaldoon M. Mhaidat ◽  
Mohammad I. Alali ◽  
Inad A. Aljarrah
Keyword(s):  
Image Processing ◽  
Low Power ◽  
Real Time ◽  
Median Filter ◽  
Verilog Hdl ◽  
Real Time Image ◽  
Placement And Routing ◽  
Canny Edge ◽  
Hardware Designs ◽  
Time Image

This paper presents efficient low-power compact hardware designs for common image processing functions including the median filter, smoothing filter, motion blurring, emboss filter, sharpening, Sobel, Roberts, and Canny edge detection. The designs were described in Verilog HDL. Xilinx ISE design suite was used for code simulation, synthesis, implementation, and chip programming. The designs were all evaluated in terms of speed, area (number of LUTs and registers), and power consumption. Post placement and routing (Post-PAR) results show that they need very small area and consume very little power while achieving good frame per second rate even for HDTV high resolution frames. This makes them suitable for real-time applications with stringent area and power budgets.

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