scholarly journals Probabilistic modeling of noise transfer characteristics in digital circuits

2011 ◽  
Vol 9 ◽  
pp. 269-272
Author(s):  
J. Schleifer ◽  
T. Coenen ◽  
A. Elkammar ◽  
T. G. Noll
Keyword(s):  
Supply Voltage ◽  
Electromagnetic Coupling ◽  
Cmos Technology ◽  
Error Rates ◽  
Process Variability ◽  
Device Scaling ◽  
Supply Noise ◽  
Significant Area ◽  
Energy Penalty ◽  
Handling Methods

Abstract. Device scaling, the driving force of CMOS technology, led to continuous decrease in the energy level representing logic states. The resulting small noise margins in combination with increasing problems regarding the supply voltage stability and process variability creates a design conflict between efficiency and reliability. This conflict is expected to rise more in future technologies. Current research approaches on fault-tolerance architectures and countermeasures at circuit level, unfortunately, cause a significant area and energy penalty without guaranteeing absence of errors. To overcome this problem, it seems to be attractive to tolerate bit errors at circuit level and employ error handling methods at higher system levels. To do this, an estimate of the bit error rate (BER) at circuit level is necessary. Due to the size of the circuits, Monte Carlo simulation suffers from impractical runtimes. Therefore the needed modeling scheme is proposed. The model allows a probabilistic estimation of error rates at circuit level taking into account statistical effects ranging from supply noise and electromagnetic coupling to process variability within reasonable runtimes.

Genetic Algorithm-based Reliability Optimization for High-Level Synthesis

2019 ◽  
Vol 28 (03) ◽  
pp. 1950039 ◽  
Author(s):  
Suleyman Tosun ◽  
Tohid Taghizad Gogjeh Yaran
Keyword(s):  
Genetic Algorithm ◽  
Integrated Circuits ◽  
Radiation Effects ◽  
Supply Voltage ◽  
Heuristic Method ◽  
Cmos Technology ◽  
Error Correcting Codes ◽  
Error Rates ◽  
Soft Error ◽  
Final Design

Soft errors (SEs) are a type of transient errors in integrated circuits (ICs) caused by radiation effects in the chips. They have become the major concern in IC design process in each CMOS technology generation since the decrease in supply voltage levels for shrinking transistor sizes makes the circuits more vulnerable than before. Previous studies generally use hardware redundancy for combinational circuits and error correcting codes for memory elements to mitigate or eliminate the SEs. However, adding extra hardware in final design may not always be possible if the design has tight area constraints. Different implementations of the same function may have different soft error rates (SERs) due to their error masking capabilities. Therefore, we can obtain various versions of the same function with different area, latency, and reliability values. Allocating the best resources to the operations of the design under area and latency constraints to optimize the overall system reliability has NP-complete time complexity. Evolutionary computing-based methods suit very well for this optimization problem. Motivated by this fact, in this paper, we present a genetic algorithm (GA)-based design method to increase the reliability of application-specific integrated circuits (ASICs). In this method, we use different versions of the same resources, each having a different area, latency, and reliability values. The goal of the GA-based optimizer is to allocate the best available resources to the application nodes to maximize the reliability of the design under tight area and latency constraints. Our experimental results show that we achieve up to 20.86% reliability improvement against a heuristic method with no additional area overhead. In order to further increase the reliability of the final design, we also propose a heuristic-based post-processing method, which adds duplicate resources to the final design without violating the constraint.

A Low-Cost RFID Regulator Insensitive to Temperature and Supply Voltage Variations

2017 ◽  
Vol 26 (10) ◽  
pp. 1750153
Author(s):  
Dawei Li ◽  
Dongsheng Liu ◽  
Xuecheng Zou ◽  
Ke Yao ◽  
Chaojian Kang ◽  
...  
Keyword(s):  
Radio Frequency Identification ◽  
Supply Voltage ◽  
Low Cost ◽  
Cmos Technology ◽  
Rejection Ratio ◽  
Supply Noise ◽  
Measurement Results ◽  
Frequency Identification ◽  
Simulation Results ◽  
Long Channel

A low-cost regulator insensitive to temperature and supply voltage variations for power management units of Radio Frequency Identification (RFID) tag chips and other batteryless devices is proposed in this paper. The commonly used regulator has poor temperature rejection ratio (TRR) and poor voltage rejection ratio (VRR). By using combination resistors and long channel transistors, the bias and regulator circuits are improved over temperature variations. A power supply rejection (PSR) enhancement branch is also added to suppress the supply noise and stabilize the bias current. The regulator is designed and fabricated in the HJTC 0.25[Formula: see text][Formula: see text]m CMOS technology. Simulation results show that this regulator achieves 0.044[Formula: see text]mV/[Formula: see text]C TRR when temperature varies from [Formula: see text]C to 70[Formula: see text]C and 1.1[Formula: see text]mV/V VRR while the supply voltage of the regulator ranges from 4 to 12[Formula: see text]V. The PSR is nearly [Formula: see text]100[Formula: see text]dB at DC. The area of this regulator is 0.102[Formula: see text]mm2 including the bias circuit. The measurement results meet simulation results well and this regulator is successfully applied in HF passive tag chips within voltage deviations of [Formula: see text] of 2.5[Formula: see text]V.

scholarly journals An 18.8–33.9 GHz, 2.26 mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2551
Author(s):  
Kwang-Il Oh ◽  
Goo-Han Ko ◽  
Jeong-Geun Kim ◽  
Donghyun Baek
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Frequency Divider ◽  
Oxide Semiconductor ◽  
Center Frequency ◽  
Radar Sensor ◽  
Frequency Locking ◽  
Current Reuse ◽  
Sensor Applications ◽  
Locking Range

An 18.8–33.9 GHz, 2.26 mW current-reuse (CR) injection-locked frequency divider (ILFD) for radar sensor applications is presented in this paper. A fourth-order resonator is designed using a transformer with a distributed inductor for wideband operating of the ILFD. The CR core is employed to reduce the power consumption compared to conventional cross-coupled pair ILFDs. The targeted input center frequency is 24 GHz for radar application. The self-oscillated frequency of the proposed CR-ILFD is 14.08 GHz. The input frequency locking range is from 18.8 to 33.8 GHz (57%) at an injection power of 0 dBm without a capacitor bank or varactors. The proposed CR-ILFD consumes 2.26 mW of power from a 1 V supply voltage. The entire die size is 0.75 mm × 0.45 mm. This CR-ILFD is implemented in a 65 nm complementary metal-oxide semiconductor (CMOS) technology.

scholarly journals High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Symmetry ◽  
2021 ◽  
Vol 13 (4) ◽  
pp. 700
Author(s):  
Yufei Zhu ◽  
Zuocheng Xing ◽  
Zerun Li ◽  
Yang Zhang ◽  
Yifan Hu
Keyword(s):  
High Performance ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Cmos Technology ◽  
Area Efficiency ◽  
Prior Art ◽  
New Radio ◽  
High Area ◽  
Significant Area ◽  
Area Efficient

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

Reliability of Metal Gate / High-k devices and its impact on CMOS technology scaling

MRS Advances ◽  
2017 ◽  
Vol 2 (52) ◽  
pp. 2973-2982 ◽  
Author(s):  
Andreas Kerber
Keyword(s):  
Dielectric Breakdown ◽  
Cmos Technology ◽  
Gate Stack ◽  
Leakage Currents ◽  
Technology Scaling ◽  
Device Scaling ◽  
Novel Device ◽  
Time Dependent Dielectric Breakdown ◽  
Bias Temperature Instability ◽  
High K

ABSTRACTMG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing.In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies.

CMOS PULSE GENERATOR FOR BPSK, OOK, PAM, AND PPM MODULATIONS

2009 ◽  
Vol 18 (03) ◽  
pp. 487-495 ◽  
Author(s):  
VINCENZO STORNELLI ◽  
GIUSEPPE FERRI ◽  
KING PACE
Keyword(s):  
Remote Control ◽  
Power Consumption ◽  
Pulse Duration ◽  
Short Range ◽  
Pulse Generator ◽  
Supply Voltage ◽  
Pulse Repetition Frequency ◽  
Cmos Technology ◽  
Single Chip ◽  
Control Applications

This work presents a single chip integrated pulse generator-modulator to be utilized in a short range wireless radio sensors remote control applications. The circuit, which can generate single pulses, modulated in BPSK, OOK, PAM, and also PPM, has been developed in a standard CMOS technology (AMS 0.35 μm). Typical pulse duration is about 1 ns while pulse repetition frequency is until 200 MHz (5 ns "chip" time). The operating supply voltage is ± 2.5 V, while the whole power consumption is about 15 mW. Post-layout parametric and corner analyses have confirmed the theoretical expectations.

Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

A 12-BIT 400-MS/s CURRENT-STEERING DAC WITH DEGLITCHING TECHNIQUE

2014 ◽  
Vol 23 (01) ◽  
pp. 1450004 ◽  
Author(s):  
XIAOBO XUE ◽  
XIAOLEI ZHU ◽  
QIFENG SHI ◽  
LENIAN HE
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Measurement Results ◽  
Voltage Swing ◽  
Current Steering Dac ◽  
Low Supply Voltage

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) employing a deglitching technique is proposed. The deglitching technique is realized by lowering the voltage swing of the control signal as well as by using a method of glitch counteraction (GC). A new switch–driver structure is designed to enable the effectiveness of the GC and provide sufficient driving capability under a low supply voltage. Moreover, the control signal's rise/fall asymmetry which increases the glitch error can be suppressed by using the proposed switch–driver structure. The 12-bit DAC is implemented in 180 nm CMOS technology. The measurement results show that the spurious free dynamic range (SFDR) at low signal frequency is 78.8 dB, and it is higher than 70 dB up to 60 MHz signal frequency at 400 MS/s. The measured INL and DNL are both less than ±0.6 LSB.

scholarly journals Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformity

2022 ◽  
Vol 6 (1) ◽  
Author(s):  
Taikyu Kim ◽  
Cheol Hee Choi ◽  
Pilgyu Byeon ◽  
Miso Lee ◽  
Aeran Song ◽  
...  
Keyword(s):  
Field Effect ◽  
Physical Vapor Deposition ◽  
High Performance ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Three Dimensional ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Wafer Scale

AbstractAchieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.

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