scholarly journals Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Technology

2014 ◽  
Vol 5 (5) ◽  
pp. 31-43 ◽  
Author(s):  
Mehdi Masoudi ◽  
Milad Mazaheri ◽  
Aliakbar Rezaei ◽  
Keivan Navi
Keyword(s):  
Carbon Nanotube ◽  
Low Power ◽  
High Speed ◽  
Full Adder ◽  
Carbon Nanotube Technology

ANALYSIS OF A NOVEL FULL ADDER DESIGNED FOR IMPLEMENTING IN CARBONE NANOTUBE TECHNOLOGY

2012 ◽  
Vol 21 (05) ◽  
pp. 1250042 ◽  
Author(s):  
MAHDIAR GHADIRY ◽  
MAHDIEH NADI ◽  
HOSEIN MOHAMMADI ◽  
ASRULNIZAM BIN ABD MANAF
Keyword(s):  
Low Power ◽  
High Speed ◽  
Full Adder ◽  
Ultra Low Power ◽  
New Approach ◽  
And Performance ◽  
Carbon Nanotube Technology ◽  
Power Delay Product ◽  
Full Swing ◽  
Very High

A novel low power-delay product full adder circuit is presented in this paper. A new approach is used in order to design full-swing full adder with low number of transistors. The proposed full adder is implemented in MOSFET-like Carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that, there are substantial improvements in both power and performance of the proposed circuit compared to latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to estimate the advantages of using carbon-based transistors in digital designs over conventional silicon technology. The proposed circuit can be applied in ultra low power and very high speed applications.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

scholarly journals A high-speed hybrid Full Adder with low power consumption

2012 ◽  
Vol 9 (24) ◽  
pp. 1900-1905
Author(s):  
Kamran Delfan Hemmati ◽  
Mojtaba Behzad Fallahpour ◽  
Abbas Golmakani ◽  
Kamyar Delfan Hemmati
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Full Adder ◽  
Low Power Consumption
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