scholarly journals CADS: Core-Aware Dynamic Scheduler for Multicore Memory Controllers

2019 ◽  
Author(s):  
Eduardo Olmedo Sanchez ◽  
Xian He Sun
Keyword(s):  
Dynamic Scheduler

Comparing SARS-CoV-2 Sequences using a Commercial Cloud with a Spot Instance Based Dynamic Scheduler

2021 ◽  
Author(s):  
Luan Teylo ◽  
Alan L. Nunes ◽  
Alba C. M. A. Melo ◽  
Cristina Boeres ◽  
Lucia Maria de A. Drummond ◽  
...  
Keyword(s):  
Dynamic Scheduler

scholarly journals Impact study of data locality on task-based applications through the Heteroprio scheduler

2019 ◽  
Vol 5 ◽  
pp. e190 ◽  
Author(s):  
Bérenger Bramas
Keyword(s):  
Heterogeneous Computing ◽  
Fast Multipole Method ◽  
Data Locality ◽  
Parallel Applications ◽  
Processing Unit ◽  
Task Distribution ◽  
Significant Performance ◽  
The Right ◽  
Dynamic Scheduler ◽  
Simple Heuristics

The task-based approach has emerged as a viable way to effectively use modern heterogeneous computing nodes. It allows the development of parallel applications with an abstraction of the hardware by delegating task distribution and load balancing to a dynamic scheduler. In this organization, the scheduler is the most critical component that solves the DAG scheduling problem in order to select the right processing unit for the computation of each task. In this work, we extend our Heteroprio scheduler that was originally created to execute the fast multipole method on multi-GPUs nodes. We improve Heteroprio by taking into account data locality during task distribution. The main principle is to use different task-lists for the different memory nodes and to investigate how locality affinity between the tasks and the different memory nodes can be evaluated without looking at the tasks’ dependencies. We evaluate the benefit of our method on two linear algebra applications and a stencil code. We show that simple heuristics can provide significant performance improvement and cut by more than half the total memory transfer of an execution.

scholarly journals Hardware RTOS: Custom Scheduler Implementation Based on Multiple Pipeline Registers and MIPS32 Architecture

Electronics ◽  
2019 ◽  
Vol 8 (2) ◽  
pp. 211 ◽  
Author(s):  
Ionel Zagan ◽  
Vasile Găitan
Keyword(s):  
Real Time ◽  
Response Speed ◽  
Real Time Control ◽  
Shared Resources ◽  
Time Control ◽  
Systems Software ◽  
Switch Operation ◽  
And Performance ◽  
Dynamic Scheduler ◽  
Time Systems

The task context switch operation, the inter-task synchronization and communication mechanisms, as well as the jitter occurred in treating aperiodic events, are crucial factors in implementing real-time operating systems (RTOS). In practice and literature, several solutions can be identified for improving the response speed and performance of real-time systems. Software implementations of RTOS-specific functions can generate significant delays, adversely affecting the deadlines required for certain applications. This paper presents an original implementation of a dedicated processor, based on multiple pipeline registers, and a hardware support for a dynamic scheduler with the following characteristics: performs unitary event management, provides access to architecture shared resources, prioritizes and executes the multiple events expected by the same task. The paper also presents a method through which interrupts are assigned to tasks. Through dedicated instructions, the integrated hardware scheduler implements tasks synchronization with multiple prioritized events, thus ensuring an efficient functioning of the processor in the context of real-time control.

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