scholarly journals 32-bit Kogge-Stone based Hybrid Adder Implemented using Standard Cells of Different Logic Families

2021 ◽  
Vol 23 (09) ◽  
pp. 196-204
Author(s):  
Hema Singaravelan ◽  
◽  
Dr. Kiran V ◽  
Keyword(s):  
Critical Role ◽  
Power Saving ◽  
Cmos Technology ◽  
Standard Cell ◽  
Design Constraints ◽  
Standard Cells

Adders performs a critical role in all computational operations, thereby optimizing them with respect to design constraints for a system is essential. In this paper, standard cells of different logic families, namely- CMOS, Pseudo NMOS, and MGDI, are designed in Cadence Design Suite Virtuoso 6.1.7 in 180nm technology and characterized using Liberate 15.1.3. The standard cell libraries thus created are then applied to 32-bit KSA (Kogge-Stone Adder) and KSA based proposed hybrid adder that are implemented in Verilog, functionally verified on Xilinx Vivado 2020.2 and synthesized on Cadence Genus 15.22. Pseudo NMOS logic shows 14.03% area savings and MGDI offers 54.43% power saving based on area per cell over the traditional CMOS technology. It is also seen that the proposed adder offers a decrease in power and delay by 32.13% and 13.75% over KSA, respectively, in CMOS logic. Further discussions are made and suitable applications for all designs are also discussed.

A Bio-inspired and Low-power 2D Machine Vision with Adaptive Machine Learning and Forgetting

2021 ◽  
Author(s):  
Akhil Dodda ◽  
Darsith Jayachandran ◽  
Shiva Subbulakshmi Radhakrishnan ◽  
Saptarshi Das
Keyword(s):  
Machine Vision ◽  
Energy Gap ◽  
Critical Role ◽  
Visual Stimuli ◽  
Bright Light ◽  
Complementary Metal Oxide Semiconductor ◽  
Active Role ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Large Area

Abstract Natural intelligence has many dimensions, and in animals, learning about the environment and making behavioral changes are some of its manifestations. In primates vision plays a critical role in learning. The underlying biological neural networks contain specialized neurons and synapses which not only sense and process the visual stimuli but also learns and adapts, with remarkable energy efficiency. Forgetting also plays an active role in learning. Mimicking the adaptive neurobiological mechanisms for seeing, learning, and forgetting can, therefore, accelerate the development of artificial intelligence (AI) and bridge the massive energy gap that exists between AI and biological intelligence. Here we demonstrate a bio-inspired machine vision based on large area grown monolayer 2D phototransistor array integrated with analog, non-volatile, and programmable memory gate-stack that not only enables direct learning, and unsupervised relearning from the visual stimuli but also offers learning adaptability under photopic (bright-light), scotopic (low-light), as well as noisy illumination conditions at miniscule energy expenditure. In short, our “all-in-one” hardware vision platform combines “sensing”, “computing” and “storage” not only to overcome the von Neumann bottleneck of conventional complementary metal oxide semiconductor (CMOS) technology but also to eliminate the need for peripheral circuits and sensors.

scholarly journals Design and Analysis of Low Power SRAM using CMOS Technology

2019 ◽  
Vol 8 (12S) ◽  
pp. 896-902
Keyword(s):  
Integrated Circuits ◽  
Power Saving ◽  
Cmos Technology ◽  
Video Data ◽  
Compression Technique ◽  
Spatial Locality ◽  
Temporal And Spatial ◽  
On Chip ◽  
Technology Nodes ◽  
Application Specific

The power consumption in commercial processors and application specific integrated circuits increases with decreasing technology nodes. Power saving techniques have become a first class design point for current and future VLSI systems. These systems employ large on-chip SRAM memories. Reducing memory leakage power while maintaining data integrity is a key criterion for modern day systems. Unfortunately, state of the art techniques like power-gating can only be applied to logic as these would destroy the contents of the memory if applied to a SRAM system. Fortunately, previous works have noted large temporal and spatial locality for data patterns in commerical processors as well as application specific ICs that work on images, audio and video data. This paper presents a novel column based Energy Compression technique that saves SRAM power by selectively turning off cells based on a data pattern. This technique is applied to study the power savings in application specific inegrated circuit SRAM memories and can also be applied for commercial processors. The paper also evaluates the effects of processing images before storage and data cluster patterns for optimizing power savings..

A Low-Power, Signal-Specific SAR ADC for Neural Sensing Applications

2018 ◽  
Vol 27 (14) ◽  
pp. 1850230 ◽  
Author(s):  
Samaneh Babayan-Mashhadi ◽  
Mona Jahangiri-Khah
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Power Saving ◽  
Cmos Technology ◽  
Sar Adc ◽  
Signal Acquisition ◽  
Quantization Scheme ◽  
Power Efficient ◽  
Sensing Applications

As power consumption is one of the major issues in biomedical implantable devices, in this paper, a novel quantization method is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs) which can save 80% power consumption in contrast to conventional structure for electroencephalogram (EEG) signal recording systems. According to the characteristics of neural signals, the principle of the proposed power saving technique was inspired such that only the difference between current input sample and the previous one is quantized, using a power efficient SAR ADC with fewer resolutions. To verify the proposed quantization scheme, the ADC is systematically modeled in Matlab and designed and simulated in circuit level using 0.18[Formula: see text][Formula: see text]m CMOS technology. When applied to neural signal acquisition, spice simulations show that at sampling rate of 25[Formula: see text]kS/s, the proposed 8-bit ADC consumes 260[Formula: see text]nW of power from 1.8[Formula: see text]V supply voltage while achieving 7.1 effective number of bits.

Multi-Bit Flip-Flop Replacement Method Optimization and Synthesis Impact

2014 ◽  
Vol 716-717 ◽  
pp. 1239-1243
Author(s):  
An Jing Wang ◽  
Yu Zhuo Fu
Keyword(s):  
Power Saving ◽  
Maximum Speed ◽  
Standard Cell ◽  
Large Area ◽  
Flip Flop ◽  
Know How ◽  
Replacement Method ◽  
Comprehensive Comparison ◽  
Method Optimization ◽  
Bit Flip

Recently, Multi-bit flip-flop usage has shown its advantage in dynamic power saving in nowadays commercial electronic design. This paper present a more comprehensive comparison of chip-level synthesis result by using single-bit flip-flop and multi-bit flip-flop standard cell and except for analyzing the power and area benefit from replacement under the maximum speed, this paper give a compromise solution to solve that using multi-bit flip-flop cannot run as the fastest as single-bit with even large area. The trade-off between a multi-bit flip-flop cell driving strength and its area when designing multi-bit standard cell that will greatly influence synthesis result as speed arise are also mentioned. Finally, this research about MBFF further usage improvements may be helpful for designers to know how to take full advantage of multi-bit flip-flops to bring about the wanted benefit.

Enabling Cell Aware Diagnosis in a Foundry for Accurate and Efficient Failure Analysis of Cell Internal Defects

2020 ◽  
Author(s):  
Rohan Deshpande ◽  
Gregory Billus ◽  
Nikitha Penmethsa ◽  
Davide Pacifico ◽  
Huaxing Tang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Turnaround Time ◽  
Internal Layer ◽  
Standard Cell ◽  
Internal Defects ◽  
Standard Cells ◽  
Quick Turnaround ◽  
Random Defects ◽  
Quick Turnaround Time

Abstract Cell aware diagnosis identifies defects within the standard cell as opposed to traditional layout aware diagnosis that identifies the failing standard cell or the area between two standard cells. In a mature technology dominated by random defects, cell aware results pinpoint the cell internal layer drastically reducing the turnaround time for failure analysis. This paper describes a method to enable cell aware diagnosis in a foundry environment, perform a volume diagnosis analysis with RCAD (fail mode pareto) and drive failure analysis with a quick turnaround time for a 14nm customer chip.

scholarly journals New voltage and temperature scalable gate delay model applied to a 14nm technology

2020 ◽  
Vol 20 (3) ◽  
pp. 1210
Author(s):  
Kenza Charafeddine ◽  
Faissal Ouardi
Keyword(s):  
Classical Method ◽  
Processing Unit ◽  
Gate Delay ◽  
Standard Cell ◽  
Delay Model ◽  
Standard Cell Library ◽  
Central Processing ◽  
Cell Library ◽  
Standard Cells

<p>The following work shows an innovative approach to model the timing of<br />standard cells. By using mathematical models instead of the classical SPICE-based characterization, a high amount of CPU (Central Processing Unit) cores is saved and less amount of data is stored. In the present work,<br />characterization of cells of a standard cell library is done in an hour whereas<br />it is done in 650 hours with the classical method. Also, a method for<br />validating and verification of the precision of the modelled data is presented<br />by comparing them on a implemented circuit. The output of implementations shows less than 3% of error between the two methods.</p>

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