scholarly journals New Built-In Self-Test Boundary Scan Architectures for Digital Integrated Circuits in Industrial Applications

2018 ◽  
Vol 182 (1) ◽  
pp. 41-55
Author(s):  
Mohamed H. ◽  
Sherif Anas ◽  
Winston Waller
Keyword(s):  
Integrated Circuits ◽  
Industrial Applications ◽  
Boundary Scan ◽  
Digital Integrated Circuits ◽  
Self Test ◽  
Built In Self Test

Built-in Self-Test for Digital Integrated Circuits

1994 ◽  
Vol 73 (2) ◽  
pp. 30-39 ◽  
Author(s):  
Vishwani D. Agrawal ◽  
Chih-Jen Lin ◽  
Paul W. Rutkowski ◽  
Shianling Wu ◽  
Yervant Zorian
Keyword(s):  
Integrated Circuits ◽  
Digital Integrated Circuits ◽  
Self Test ◽  
Built In Self Test

Boundary scan with built-in self-test

1989 ◽  
Vol 6 (1) ◽  
pp. 36-44 ◽  
Author(s):  
C.S. Gloster ◽  
F. Brglez
Keyword(s):  
Boundary Scan ◽  
Self Test ◽  
Built In Self Test

scholarly journals A Built-in Self-Test System for External DRAM

2020 ◽  
pp. 80-87
Author(s):  
Gor Abgaryan
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
High Efficiency ◽  
Random Access ◽  
Test System ◽  
Mass Storage ◽  
Access Memory ◽  
Yield And Quality ◽  
Self Test ◽  
Built In Self Test

In the fast-growing Integrated Circuits (IC) industry, memory is one of the few keys to have systems with improved and fast performance. Only one transistor and a capacitor are required for Dynamic Random-Access Memory (DRAM) bit. It is widely used for mass storage. Although the high-efficiency tests are performed to provide the reliability of the memories, maintaining acceptable yield and quality is still the most critical task. To perform a high-speed effective test of DRAM memories, a built-in self-test (BIST) mechanism is proposed.

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