Clock Power Analysis of Low Power Clock Gated Arithmetic Logic Unit on Different FPGA

2014 ◽  
Author(s):  
Nidhi Gupta
Keyword(s):  
Low Power ◽  
Power Analysis ◽  
Arithmetic Logic Unit ◽  
Logic Unit

scholarly journals A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 6876-6889 ◽  
Author(s):  
Prashanth Barla ◽  
Vinod Kumar Joshi ◽  
Somashekara Bhat
Keyword(s):  
Low Power ◽  
Cmos Circuit ◽  
Arithmetic Logic Unit ◽  
Logic Unit

scholarly journals A Novel Approach to Design 2-bit Binary Arithmetic Logic Unit (ALU) Circuit Using Optimized 8:1 Multiplexer with Reversible logic

2015 ◽  
Vol 11 (2) ◽  
pp. 104
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari
Keyword(s):  
Low Power ◽  
Optical Computing ◽  
Reversible Logic ◽  
Low Loss ◽  
Arithmetic Logic Unit ◽  
Novel Approach ◽  
Cmos Design ◽  
Binary Arithmetic ◽  
Low Power Cmos ◽  
Logic Unit

Reversible circuit designing is the area where researchers are focussing more and more for the generation of low loss digital system designs. Researchers are using the concept of Reversible Logic in many areas such as Nanotechnology, low loss computing, optical computing, low power CMOS design etc. Here we have proposed a novel design approach for a 2-bit binary Arithmetic Logic Unit (ALU) using optimized 8:1 multiplexer circuit with reversible logic concept [1]. This ALU circuit can perform complement, transfer, addition, subtraction, multiplication, OR, XOR, NAND functions on given values. The ALU circuit has been simulated on Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency. This 2-bit ALU using reversible logic is useful for the designs of low power loss systems.

scholarly journals A Novel Design and Evaluation of a Low Power Efficient Fault-Tolerant Reversible ALU Using QCA: Applications of Nanoelectronics

2021 ◽  
Author(s):  
Mary Swarna Latha Gade ◽  
Rooban S
Keyword(s):  
Low Power ◽  
High Speed ◽  
Fault Tolerant ◽  
Logic Gates ◽  
Reversible Logic ◽  
Functional Verification ◽  
Logical Operations ◽  
Arithmetic Logic Unit ◽  
Reversible Alu ◽  
Logic Unit

Abstract Reversible logic based on Quantum-dot Cellular Automata (QCA) is the most requirement for achieving nano-scale architecture that promises significantly high device integration density, high-speed calculation, and low power consumption. The arithmetic logic unit (ALU) is the significant component of a processor for processing and computing. The primary objective of this work is to develop a multi-layer fault-tolerant arithmetic logic unit using reversible logic in QCA technology. Additionally, the reversible ALU has divided into arithmetic (RAU) and a logic unit (RLU). A reversible 2:1 MUX using the Fredkin gate has been implemented to select either the arithmetic or logical operations. Besides, to improve the efficiency of arithmetic operations, a novel QCA reversible full adder is implemented. To build the ALU, fault-tolerant reversible logic gates are used. The proposed reversible multilayer QCA ALU is designed to carry out eight arithmetic and sixteen logical operations with a minimum number of gates, constant inputs, and garbage outputs compared to the existing works. The functional verification and simulation of the presented circuits are assessed by the QCADesigner tool.

Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit

2017 ◽  
Vol 9 (4) ◽  
pp. 04018-1-04018-4
Author(s):  
K. Nehru ◽  
◽  
T. Nagarjuna ◽  
G. Vijay ◽  
◽  
...  
Keyword(s):  
Comparative Analysis ◽  
Arithmetic Logic Unit ◽  
Logic Unit
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