Comparison of Leakage Power Reduction Techniques in 65nm Technologies

Vikas Singhai; Saima Ayyub; Paresh Rawat

doi:10.5120/ijca2016907962

Comparison of Leakage Power Reduction Techniques in 65nm Technologies

International Journal of Computer Applications ◽

10.5120/ijca2016907962 ◽

2016 ◽

Vol 134 (8) ◽

pp. 28-32

Author(s):

Vikas Singhai ◽

Saima Ayyub ◽

Paresh Rawat

Keyword(s):

Power Reduction ◽

Leakage Power ◽

Reduction Techniques

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Effect of leakage power reduction techniques on combinational circuits

2015 Online International Conference on Green Engineering and Technologies (IC-GET) ◽

10.1109/get.2015.7453862 ◽

2015 ◽

Author(s):

M. Manoranjani ◽

T. Ravi ◽

R. Ramya

Keyword(s):

Power Reduction ◽

Leakage Power ◽

Combinational Circuits ◽

Reduction Techniques

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An Overview of Various Leakage Power Reduction Techniques in Deep Submicron Technologies

2015 International Conference on Computing Communication Control and Automation ◽

10.1109/iccubea.2015.196 ◽

2015 ◽

Cited By ~ 3

Author(s):

Varsha Bendre ◽

A.K. Kureshi

Keyword(s):

Deep Submicron ◽

Power Reduction ◽

Leakage Power ◽

Reduction Techniques

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Analysis of leakage power reduction techniques in digital circuits

2011 Annual IEEE India Conference ◽

10.1109/indcon.2011.6139374 ◽

2011 ◽

Cited By ~ 4

Author(s):

Anup Jalan ◽

Mamta Khosla

Keyword(s):

Digital Circuits ◽

Power Reduction ◽

Leakage Power ◽

Reduction Techniques

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Leakage Power Reduction Techniques for Nanoscale CMOS VLSI Systems and Effect of Technology Scaling on Leakage Power

International Journal of Engineering Trends and Technology ◽

10.14445/22315381/ijett-v46p254 ◽

2017 ◽

Vol 46 (6) ◽

pp. 309-315

Author(s):

P Prashanti ◽

◽

A.Shra vya ◽

K.Dhruthi Vasista ◽

U.Pran athi ◽

...

Keyword(s):

Power Reduction ◽

Leakage Power ◽

Technology Scaling ◽

Nanoscale Cmos ◽

Reduction Techniques ◽

Cmos Vlsi

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Modeling and simulation of high level leakage power reduction techniques for 7T SRAM cell design

10.1063/1.4751561 ◽

2012 ◽

Cited By ~ 1

Author(s):

Shyam Akashe ◽

Sushil Bhushan ◽

Sanjay Sharma

Keyword(s):

Modeling And Simulation ◽

Power Reduction ◽

Leakage Power ◽

Cell Design ◽

Reduction Techniques ◽

Sram Cell ◽

High Level

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Performance analysis of asynchronous dual mode logic using leakage power reduction techniques

2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS) ◽

10.1109/iciiecs.2015.7193149 ◽

2015 ◽

Author(s):

Balamurugan V

Keyword(s):

Performance Analysis ◽

Power Reduction ◽

Leakage Power ◽

Dual Mode ◽

Reduction Techniques

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Leakage Power Reduction Techniques in Deep Submicron Technologies for VLSI Applications

Procedia Engineering ◽

10.1016/j.proeng.2012.01.976 ◽

2012 ◽

Vol 30 ◽

pp. 1163-1170 ◽

Cited By ~ 5

Author(s):

M.Geetha Priya ◽

K. Baskaran ◽

D. Krishnaveni

Keyword(s):

Deep Submicron ◽

Power Reduction ◽

Leakage Power ◽

Reduction Techniques

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Analysis and comparison of leakage power reduction techniques in CMOS circuits

2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN) ◽

10.1109/spin.2015.7095351 ◽

2015 ◽

Cited By ~ 5

Author(s):

Smita Singhal ◽

Nidhi Gaur ◽

Anu Mehra ◽

Pradeep Kumar

Keyword(s):

Power Reduction ◽

Leakage Power ◽

Cmos Circuits ◽

Reduction Techniques

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Analysis and Comparison of Leakage Power Reduction Techniques for VLSI Design

2021 International Conference on Computer Communication and Informatics (ICCCI) ◽

10.1109/iccci50826.2021.9402315 ◽

2021 ◽

Author(s):

Anirudh Raghunath ◽

Shikha Bathla

Keyword(s):

Vlsi Design ◽

Power Reduction ◽

Leakage Power ◽

Reduction Techniques

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A Novel Approach for Leakage Power Reduction Techniques in 65nm Technologies

International Journal of VLSI Design & Communication Systems ◽

10.5121/vlsic.2014.5301 ◽

2014 ◽

Vol 5 (3) ◽

pp. 01-11 ◽

Cited By ~ 2

Author(s):

Ajay Kumar Dadoria ◽

Kavita Khare

Keyword(s):

Power Reduction ◽

Leakage Power ◽

Reduction Techniques ◽

Novel Approach

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