Modeling and simulation of high level leakage power reduction techniques for 7T SRAM cell design

2012 ◽  
Author(s):  
Shyam Akashe ◽  
Sushil Bhushan ◽  
Sanjay Sharma
Keyword(s):  
Modeling And Simulation ◽  
Power Reduction ◽  
Leakage Power ◽  
Cell Design ◽  
Reduction Techniques ◽  
Sram Cell ◽  
High Level

scholarly journals 8T SRAM Cell Design for Dynamic and Leakage Power Reduction

2013 ◽  
Vol 71 (9) ◽  
pp. 43-48 ◽  
Author(s):  
Maisagalla Gopal ◽  
D Siva Sankar Prasad ◽  
Balwinder Raj
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Cell Design ◽  
Sram Cell

scholarly journals Comparative analysis of SRAM cell with leakage power reduction approaches

2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Power Saving ◽  
Vital Role ◽  
Power Reduction ◽  
Leakage Power ◽  
Access Time ◽  
Chip Area ◽  
Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

scholarly journals Comparison of Leakage Power Reduction Techniques in 65nm Technologies

2016 ◽  
Vol 134 (8) ◽  
pp. 28-32
Author(s):  
Vikas Singhai ◽  
Saima Ayyub ◽  
Paresh Rawat
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Reduction Techniques
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