FPGA Implementation of Programmable Systolic Array for Sinusoidal Sequence Generation

Noor Kareem

doi:10.5120/cae2016652048

FPGA Implementation of Programmable Systolic Array for Sinusoidal Sequence Generation

Communications on Applied Electronics ◽

10.5120/cae2016652048 ◽

2016 ◽

Vol 5 (1) ◽

pp. 6-12

Author(s):

Noor Kareem

Keyword(s):

Systolic Array ◽

Fpga Implementation ◽

Sequence Generation

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Resource and Performance Evaluations of Fixed Point QRD-RLS Systolic Array through FPGA Implementation

IEICE Transactions on Communications ◽

10.1093/ietcom/e91-b.4.1068 ◽

2008 ◽

Vol E91-B (4) ◽

pp. 1068-1075 ◽

Cited By ~ 1

Author(s):

Y. YOKOYAMA ◽

M. KIM ◽

H. ARAI

Keyword(s):

Fixed Point ◽

Systolic Array ◽

Fpga Implementation ◽

Performance Evaluations ◽

And Performance

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An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDIC

2014 International Conference on Field-Programmable Technology (FPT) ◽

10.1109/fpt.2014.7082764 ◽

2014 ◽

Cited By ~ 3

Author(s):

Jianfeng Zhang ◽

Paul Chow ◽

Hengzhu Liu

Keyword(s):

Systolic Array ◽

Qr Decomposition ◽

Fpga Implementation ◽

Array Architecture

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Design and FPGA Implementation of Systolic Array Architecture for Matrix Multiplication

International Journal of Computer Applications ◽

10.5120/3084-4222 ◽

2011 ◽

Vol 26 (3) ◽

pp. 18-22 ◽

Cited By ~ 6

Author(s):

Mahendra Vucha ◽

Arvind Rajawat

Keyword(s):

Systolic Array ◽

Matrix Multiplication ◽

Fpga Implementation ◽

Array Architecture

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A truly two-dimensional systolic array FPGA implementation of QR decomposition

ACM Transactions on Embedded Computing Systems ◽

10.1145/1596532.1596535 ◽

2009 ◽

Vol 9 (1) ◽

pp. 1-17 ◽

Cited By ~ 15

Author(s):

Xiaojun Wang ◽

Miriam Leeser

Keyword(s):

Systolic Array ◽

Qr Decomposition ◽

Fpga Implementation ◽

Two Dimensional

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FPGA implementation of a linear systolic array for speech recognition based on HMM

2010 The 2nd International Conference on Computer and Automation Engineering (ICCAE) ◽

10.1109/iccae.2010.5451202 ◽

2010 ◽

Cited By ~ 5

Author(s):

Mohammad Mosleh ◽

Saeed Setayeshi ◽

M Mehdi Lotfinejad ◽

Ali Mirshekari

Keyword(s):

Speech Recognition ◽

Systolic Array ◽

Fpga Implementation

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A low-power systolic array-based adaptive Viterbi decoder and its FPGA implementation

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. ◽

10.1109/iscas.2003.1205960 ◽

2003 ◽

Cited By ~ 3

Author(s):

Man Guo ◽

M. Omair Ahmad ◽

M.N.S. Swamy ◽

Chunyan Wang

Keyword(s):

Low Power ◽

Systolic Array ◽

Fpga Implementation ◽

Viterbi Decoder

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Efficient FPGA implementation of a High throughput systolic array QR-decomposition algorithm

2011 Conference Record of the Forty Fifth Asilomar Conference on Signals, Systems and Computers (ASILOMAR) ◽

10.1109/acssc.2011.6190140 ◽

2011 ◽

Cited By ~ 6

Author(s):

Matthias Abels ◽

Till Wiegand ◽

Steffen Paul

Keyword(s):

High Throughput ◽

Systolic Array ◽

Qr Decomposition ◽

Fpga Implementation ◽

Decomposition Algorithm

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A fully pipelined systolic array for sinusoidal sequence generation

IEEE Transactions on Computers ◽

10.1109/tc.2006.64 ◽

2006 ◽

Vol 55 (5) ◽

pp. 636-639

Author(s):

N. Alwan

Keyword(s):

Systolic Array ◽

Sequence Generation

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FPGA implementation and resource utilization for QRD-RLS systolic array for signal processing applications

TENCON 2009 - 2009 IEEE Region 10 Conference ◽

10.1109/tencon.2009.5395991 ◽

2009 ◽

Cited By ~ 4

Author(s):

K. R. Santha ◽

Bharani Chakravarthy Chava ◽

K. Bragadishwaran ◽

K. Chandru

Keyword(s):

Signal Processing ◽

Resource Utilization ◽

Systolic Array ◽

Fpga Implementation

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Efficient FPGA implementation of qr decomposition using a systolic array architecture

Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays - FPGA '08 ◽

10.1145/1344671.1344718 ◽

2008 ◽

Cited By ~ 1

Author(s):

Xiaojun Wang ◽

Miriam Leeser

Keyword(s):

Systolic Array ◽

Qr Decomposition ◽

Fpga Implementation ◽

Array Architecture

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