A low-power systolic array-based adaptive Viterbi decoder and its FPGA implementation

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. ◽

10.1109/iscas.2003.1205960 ◽

2003 ◽

Cited By ~ 3

Author(s):

Man Guo ◽

M. Omair Ahmad ◽

M.N.S. Swamy ◽

Chunyan Wang

Keyword(s):

Low Power ◽

Systolic Array ◽

Fpga Implementation ◽

Viterbi Decoder

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FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications ◽

10.1109/tcsi.2004.838266 ◽

2005 ◽

Vol 52 (2) ◽

pp. 350-365 ◽

Cited By ~ 19

Author(s):

Man Guo ◽

M.O. Ahmad ◽

M.N.S. Swamy ◽

Chunyan Wang

Keyword(s):

Low Power ◽

Systolic Array ◽

Viterbi Decoder ◽

Fpga Design ◽

Design And Implementation

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FPGA Implementation of 413.121 MHz and 11.34 mW High Speed Low Power Viterbi Decoder

International Journal of Modeling and Optimization ◽

10.7763/ijmo.2013.v3.226 ◽

2013 ◽

pp. 15-19 ◽

Cited By ~ 1

Author(s):

Pooran Singh ◽

Santosh Kr. Vishvakarma

Keyword(s):

Low Power ◽

High Speed ◽

Fpga Implementation ◽

Viterbi Decoder

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FPGA Implementation of High Speed and Low Power Viterbi Decoder Using Reverse Algorithm of Convolution Encoder

Journal of Computational and Theoretical Nanoscience ◽

10.1166/jctn.2017.7042 ◽

2017 ◽

Vol 14 (12) ◽

pp. 5957-5962

Author(s):

K Ramesh ◽

S Sudha

Keyword(s):

Low Power ◽

High Speed ◽

Fpga Implementation ◽

Viterbi Decoder

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Low-Power Systolic Array Viterbi Decoder Implementation With A Clock-gating Method

The KIPS Transactions PartA ◽

10.3745/kipsta.2005.12a.1.001 ◽

2005 ◽

Vol 12A (1) ◽

pp. 1-6

Author(s):

Je-Hyuk Ryu ◽

Jun-Dong Cho

Keyword(s):

Low Power ◽

Systolic Array ◽

Viterbi Decoder ◽

Clock Gating ◽

Gating Method

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Low power, dynamically reconfigurable, memoryless systolic array based architecture for Viterbi decoder

2011 International Conference on Energy, Automation and Signal ◽

10.1109/iceas.2011.6147135 ◽

2011 ◽

Cited By ~ 1

Author(s):

A. K. Mishra ◽

P. P. Jiju

Keyword(s):

Low Power ◽

Systolic Array ◽

Viterbi Decoder ◽

Dynamically Reconfigurable

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Realization of security aware low power sensor node deployment using fpga implementation

Materials Today Proceedings ◽

10.1016/j.matpr.2021.01.886 ◽

2021 ◽

Author(s):

S. Murugeswari ◽

G. Mahendran ◽

M. Periyasamy ◽

N. Karthika Devi ◽

V. Kamila Nasrin ◽

...

Keyword(s):

Low Power ◽

Sensor Node ◽

Fpga Implementation ◽

Node Deployment ◽

Power Sensor

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FPGA implementation of a configurable viterbi decoder for software radio receiver

2009 IEEE AUTOTESTCON ◽

10.1109/autest.2009.5314063 ◽

2009 ◽

Cited By ~ 3

Author(s):

Sherif Welsen Shaker ◽

Salwa Hussien Elramly ◽

Khaled Ali Shehata

Keyword(s):

Software Radio ◽

Fpga Implementation ◽

Radio Receiver ◽

Viterbi Decoder

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FPGA Implementation of Programmable Systolic Array for Sinusoidal Sequence Generation

Communications on Applied Electronics ◽

10.5120/cae2016652048 ◽

2016 ◽

Vol 5 (1) ◽

pp. 6-12

Author(s):

Noor Kareem

Keyword(s):

Systolic Array ◽

Fpga Implementation ◽

Sequence Generation

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Low-power bit-serial Viterbi decoder for next generation wide-band CDMA systems

1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258) ◽

10.1109/icassp.1999.758298 ◽

1999 ◽

Cited By ~ 1

Author(s):

H. Suzuki ◽

Yun-Nan Chang ◽

K.K. Parhi

Keyword(s):

Low Power ◽

Wide Band ◽

Viterbi Decoder ◽

Next Generation ◽

Cdma Systems ◽

Bit Serial

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A high-speed low-power pipelined Viterbi Decoder: breaking the ACS-bottleneck

The 2010 International Conference on Green Circuits and Systems ◽

10.1109/icgcs.2010.5543044 ◽

2010 ◽

Cited By ~ 7

Author(s):

Kelvin Yi-Tse Lai

Keyword(s):

Low Power ◽

High Speed ◽

Viterbi Decoder

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