scholarly journals FPGA Implementation of Interrupt Controller (8259) by using Verilog HDL

2012 ◽  
Vol 48 (6) ◽  
pp. 12-19
Author(s):  
L. PadmaSree ◽  
Bekkam Satheesh ◽  
N. Dhanalakshmi
Keyword(s):  
Fpga Implementation ◽  
Verilog Hdl

FPGA Implementation of Low Power Digital QPSK Modulator Using Verilog HDL

2013 ◽  
Vol 13 (3) ◽  
pp. 385-392 ◽  
Author(s):  
Asraf Mohamed Moubark ◽  
Mohd Alauddin Mohd Ali ◽  
Hilmi Sanusi ◽  
Sawal Md. Ali
Keyword(s):  
Low Power ◽  
Fpga Implementation ◽  
Verilog Hdl

Research and Realization of Key Algorithm of ADS-B Overlapping Test

2011 ◽  
Vol 403-408 ◽  
pp. 1555-1559
Author(s):  
Yu Yang ◽  
Chao Zhang
Keyword(s):  
Fpga Implementation ◽  
Verilog Hdl ◽  
Unique Character ◽  
Implementation Scheme

How to recognize the ADS-B messages is the key point of ADS-B receiver, and the preamble is the unique character of ADS-B messages. This paper describes a method for the overlapping test of the preamble detection. The FPGA implementation scheme is given in detail and the verilog HDL codes of this design is accomplished. The simulation result indicates that this method is viable and can detect the overlapping rapidly and accurately.

FPGA Implementation of Park-Miller Algorithm to Generate Sequence of 32-Bit Pseudo Random Key for Encryption and Decryption of Plain Text

2013 ◽  
Vol 2 (3) ◽  
pp. 99
Author(s):  
Bharatesh N ◽  
Rohith S
Keyword(s):  
High Speed ◽  
Random Number ◽  
Random Number Generator ◽  
Digital Circuit ◽  
Fpga Implementation ◽  
Random Numbers ◽  
Verilog Hdl ◽  
Plain Text ◽  
Booth Multiplier ◽  
Pseudo Random Number

There are many problems arises in randomized algorithms whose solutions are fundamentally based on assumptions that pure random numbers exist, so pseudo-random number generators can imitate randomness sufficiently well for most applications. The proposed scheme is a FPGA implementation of Park-Miller Algorithm for generating sequence of Pseudo-Random keys. The properties like High speed, low power and flexibility of designed PRNG(Pseudo Random Number Generator) makes any digital circuit faster and smaller. The algorithm uses a PRNG Module, it contains 32-bit Booth Multiplier, 32-bit Floating point divider and a FSM module. After generating a sequence of 32-bit Pseudo-Random numbers we have used these numbers as a key to Encrypt 128-bit plain text to become a cipher text and by using the same key to decrypt the encrypted data to get original Plain text. The Programming is done in Verilog-HDL, successfully synthesized and implemented in XILINX Spartan 3E FPGA kit.

scholarly journals FPGA Implementation of 8-Bit Vedic Multiplier for DIT-FFT Application Using Urdhva Tiryagbhyam Sutra

2021 ◽  
pp. 156-165
Author(s):  
Rohith S ◽  
Kasetty Ram Babu ◽  
Chandrashekar M N
Keyword(s):  
Software Tool ◽  
Fpga Implementation ◽  
Verilog Hdl ◽  
Booth Multiplier ◽  
Wallace Tree ◽  
Vedic Multiplier ◽  
Array Multiplier ◽  
Wallace Tree Multiplier

This paper discusses FPGA Implementation of 8-Bit Vedic Multiplier and DIT-FFT Application Using Urdhva Tiryagbhyam Sutra. Initially 8-bit Vedic multiplier performance is compared with existing multiplier such as i) Wallace tree multiplier ii) Array multiplier iii) Booth multiplier. In this work Urdhva Tiryagbhyam (upright and across) Vedic sutra is used for multiplier design which provides better performance and consumes smaller time for computation. In this work, Modified Carry Save Adder (MCSA) is used to compute the sum of partially generated products. Further the multiplier is It reduces the computational delay towards the addition of unfinished products. The proposed design uses the Verilog HDL to develop the algorithm. The XILINX 14.7 software tool is used to simulate and synthesize the code. The proposed design is used for DIT FFT application.

scholarly journals FPGA Implementation of Mean Shift Algorithm for Real Time Image Segmentation

2019 ◽  
Vol 9 (2) ◽  
pp. 3298-3304
Keyword(s):  
Mean Shift ◽  
Fpga Implementation ◽  
Verilog Hdl ◽  
Mean Shift Algorithm ◽  
Real Time Image ◽  
Machine Learning Applications ◽  
Speed Up ◽  
The Mean ◽  
The Look ◽  
Time Image

Clustering is one of the major steps in image analysis. To speed up the analysis, FPGA implementation of Mean shift algorithm is proposed. The proposed architecture computes the Mean shift operation by using power of two approximations (POTA) for linearization of Gaussian distribution. Also general approach for indexing the window is proposed for selecting the kernel size. The architecture is developed using Verilog HDL and is simulated using Xilinx ISim simulator and synthesized using Virtex 6 FPGA. The Look up table or LUT utilization when the number of input pixels that can be simultaneously processed is varied and hardware cost is analysed. The architecture designed can process four pixels simultaneously with a maximum frequency of 30MHz. The analysis shows that the number of image frames that can be processed vary from 73 to 122 frames per second. This clearly indicates that the developed architecture can be used for various machine learning applications.

FPGA Based Implementation of Semi-Fragile Watermarking Algorithm

2012 ◽  
Vol 532-533 ◽  
pp. 1419-1423
Author(s):  
Fang Ming Liu ◽  
Xiao Zhong Pan
Keyword(s):  
Real Time ◽  
Hardware Implementation ◽  
Digital Camera ◽  
Fpga Implementation ◽  
Fragile Watermarking ◽  
Invariant Property ◽  
Verilog Hdl ◽  
Time Performance ◽  
Dct Coefficients

This paper presents an FPGA implementation of a semi-fragile watermarking-based algorithm for a digital camera. The architecture of digital authentication camera is discussed and a semi-fragile watermarking algorithm based the invariant property of DCT coefficients quantization is designed which can survive a certain amount of compression. The components of a digital camera and the watermarking algorithm are described in Verilog HDL and implemented on the DE2-70 board. The results shown that the hardware implementation can provide real time performance and resist off-line attacks compare with the software-assisted solution.

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