scholarly journals FPGA Implementation of 8-Bit Vedic Multiplier for DIT-FFT Application Using Urdhva Tiryagbhyam Sutra

2021 ◽  
pp. 156-165
Author(s):  
Rohith S ◽  
Kasetty Ram Babu ◽  
Chandrashekar M N
Keyword(s):  
Software Tool ◽  
Fpga Implementation ◽  
Verilog Hdl ◽  
Booth Multiplier ◽  
Wallace Tree ◽  
Vedic Multiplier ◽  
Array Multiplier ◽  
Wallace Tree Multiplier

This paper discusses FPGA Implementation of 8-Bit Vedic Multiplier and DIT-FFT Application Using Urdhva Tiryagbhyam Sutra. Initially 8-bit Vedic multiplier performance is compared with existing multiplier such as i) Wallace tree multiplier ii) Array multiplier iii) Booth multiplier. In this work Urdhva Tiryagbhyam (upright and across) Vedic sutra is used for multiplier design which provides better performance and consumes smaller time for computation. In this work, Modified Carry Save Adder (MCSA) is used to compute the sum of partially generated products. Further the multiplier is It reduces the computational delay towards the addition of unfinished products. The proposed design uses the Verilog HDL to develop the algorithm. The XILINX 14.7 software tool is used to simulate and synthesize the code. The proposed design is used for DIT FFT application.

scholarly journals VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

2021 ◽  
Vol 14 (1) ◽  
pp. 22-31
Author(s):  
Kommalapati Monica ◽  
◽  
Dereddy Anuradha ◽  
Syed Rasheed ◽  
Barnala Shereesha ◽  
...  
Keyword(s):  
Power Consumption ◽  
Field Programmable Gate Array ◽  
Finite Impulse Response ◽  
Research Work ◽  
Industrial Applications ◽  
Booth Multiplier ◽  
Wallace Tree ◽  
Look Up Table ◽  
Field Programmable ◽  
Wallace Tree Multiplier

Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

scholarly journals Implementation of time efficient hybrid multiplier for FFT computation

2018 ◽  
Vol 7 (2.7) ◽  
pp. 409 ◽  
Author(s):  
R Nikhil ◽  
G V. S. Veerendra ◽  
J Rahul M. S. Sri Harsha ◽  
Dr V. S. V. Prabhakar
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
Vlsi Circuits ◽  
Low Power Consumption ◽  
Chip Area ◽  
Booth Multiplier ◽  
Low Delay ◽  
Wallace Tree ◽  
Wallace Tree Multiplier ◽  
Carry Save Adders

Now a days in designing a VLSI circuits we are coming across many problems such as high power intake, delay and large utilization of chip area in order to overcome these problems a new architectures are developed. In our project we deals with FFT computation which internally involves series of multiplication and addition therefore requirement of efficient multipliers is needed and therefore we come across two high speed improved multipliers Booth multiplier and Wallace tree multiplier which are good in terms of power efficiency and low output delay. The main aim of our project involves hybridizing the both Wallace multiplier and Booth multiplier which yields low delay and low power consumption than compared to individual multipliers. The Booth multiplier is used for reduction of partial products and for addition operations carry save adders is used in Wallace tree multipliers and thus hybrid is designed by combining both the algorithms which in turn produces better results and they can be observed in comparisons tabular column in our documentation. These multipliers can be designed in many ways such using cmos layout techniques and also using Verilog programming and we have chosen Verilog programming which requires Xilinx software and codes are developed in gate level design model for the respective multiplier models and the results will be tabulated.  

scholarly journals Implementation of Data Security with Wallace Tree Approach Using Elliptical Curve Cryptography on FPGA

2021 ◽  
Vol 12 (6) ◽  
pp. 1546-1553
Author(s):  
Thammaneni Snehitha Reddy, Y. David Solomon Raju
Keyword(s):  
Digital Signature ◽  
Data Security ◽  
Elliptic Curve Cryptography ◽  
Time Complexity ◽  
Energy Demand ◽  
Wallace Tree ◽  
Vedic Multiplier ◽  
Field Efficiency ◽  
Wallace Tree Multiplier ◽  
Tree Approach

The growth of computing resources and parallel computing has led to significant needs for efficient cryptosystems over the last decade. Elliptic Curve Cryptography (ECC) provides faster computation over other asymmetric cryptosystems such as RSA and greater security. For many cryptography operations, ECC can be used: hidden key exchange, message encryption, and digital signature. There is thus a trade-off between safety and efficiency with regard to speed, area and power requirements. This paper provides a good ECC approach to encryption by replacing the Vedic multiplier (16 bit) with the Wallace tree multiplier with an improved output (128 bit). The proposed design processes data recurringly with less volume, less power consumption and greater velocity, in addition to improving efficiency. Using Xilinx 2015.2 software, the entire proposed design is synthesized and simulated and implemented on the ZYNQ FPGA Board. Compared with previous implementations, a significant improvement in field efficiency, time complexity and energy demand is demonstrated by the proposed design.

scholarly journals Implementation of 64 Bit Complex Floating-Point Multiplier on FPGA using Vedic Mathematics Sutra- Urdhva Tiryagbhyam

2020 ◽  
Vol 9 (4) ◽  
pp. 2986-2989
Keyword(s):  
System Performance ◽  
Communication Systems ◽  
Complex Multiplication ◽  
Digital Signal ◽  
Floating Point ◽  
Verilog Hdl ◽  
Low Area ◽  
Booth Multiplier ◽  
Vedic Multiplier ◽  
Ripple Carry Adder

Multipliers play crucial role in present days in the area of digital signal processing and in communication systems applications. The entire system performance depends on speed area and power of the multipliers. In our paper, we developed a 64x64 bit complex floating-point multiplier with 64bit IEEE 754 format multipliers having less delay. Vedic multiplier of ripple carry adder based is suggested for mantissa multiplication in IEEE 754 format. Suggested Vedic multiplier uses historic Vedic Indian mathematics sutra called UrdhvaTiryagbhyam for Vedic multiplication. The architecture Proposed for 64x64 bit complex floating-point multiplier is in Xilinx ISE 14.2 FPGA navigator in Verilog HDL. Eventually, the outcomes of the suggested multiplier will differentiate with traditional booth multiplier and array multiplier which represents clearly that complex multiplication using suggested architecture gives less delay, power and low area.

FPGA Implementation of Park-Miller Algorithm to Generate Sequence of 32-Bit Pseudo Random Key for Encryption and Decryption of Plain Text

2013 ◽  
Vol 2 (3) ◽  
pp. 99
Author(s):  
Bharatesh N ◽  
Rohith S
Keyword(s):  
High Speed ◽  
Random Number ◽  
Random Number Generator ◽  
Digital Circuit ◽  
Fpga Implementation ◽  
Random Numbers ◽  
Verilog Hdl ◽  
Plain Text ◽  
Booth Multiplier ◽  
Pseudo Random Number

There are many problems arises in randomized algorithms whose solutions are fundamentally based on assumptions that pure random numbers exist, so pseudo-random number generators can imitate randomness sufficiently well for most applications. The proposed scheme is a FPGA implementation of Park-Miller Algorithm for generating sequence of Pseudo-Random keys. The properties like High speed, low power and flexibility of designed PRNG(Pseudo Random Number Generator) makes any digital circuit faster and smaller. The algorithm uses a PRNG Module, it contains 32-bit Booth Multiplier, 32-bit Floating point divider and a FSM module. After generating a sequence of 32-bit Pseudo-Random numbers we have used these numbers as a key to Encrypt 128-bit plain text to become a cipher text and by using the same key to decrypt the encrypted data to get original Plain text. The Programming is done in Verilog-HDL, successfully synthesized and implemented in XILINX Spartan 3E FPGA kit.

An Efficient Design for Area-Efficient Truncated Adaptive Booth Multiplier for Signal Processing Applications

2020 ◽  
pp. 2150037
Author(s):  
S. Radhakrishnan ◽  
Rakesh Kumar Karn ◽  
T. Nirmalraj
Keyword(s):  
Signal Processing ◽  
Digital Signal ◽  
Partial Product ◽  
Efficient Design ◽  
Verilog Hdl ◽  
Booth Multiplier ◽  
Vedic Multiplier ◽  
Product Array ◽  
Processing Architecture ◽  
State Of Art

In digital signal processing (DSP), the most valuable elements of processing architecture are multiplier. The conventional partial products array is to create extra rows and columns. Generally, the fixed multiplication products are truncated to [Formula: see text] bits. In this paper, we introduced an adaptive booth multiplier concept, which is based on truncated multiplication procedure. The extra partial product array is to create the complexities. In the higher order of partial product array, the deletion of LSB and the nongeneration of initial products are achieved. We added compensation bits at the appropriate retained bit position to minimize the error due to nongeneration and omission. Here, our proposed work is used to reduce the overhead and the complexity of partial product array. The proposed concept architecture is implemented in Verilog HDL software; also the design of RTL is manufactured. For experimental work, the bit multiplication of [Formula: see text] with 8, 10, 12, 14 and 16 bits is used. The proposed method of truncated based adaptive booth encoding has shown the lower value results of area, delay and power consumption. The error performances are executed by various error normalizations. Finally, the proposed concept performance is checked with various state-of-art multiplier methodologies such as carry width multiplier, Vedic multiplier, voltage-mode multiplier and Wallace multiplier. In every bit value, the proposed booth encoding multiplier delivers better and optimal performance result.

scholarly journals An Efficient Design Approach of ROI Based DWT Using Vedic and Wallace Tree Multiplier on FPGA Platform

2019 ◽  
Vol 9 (4) ◽  
pp. 2433
Author(s):  
Vijaya SM ◽  
Suresh K
Keyword(s):  
Performance Metrics ◽  
Brain Mri ◽  
Region Of Interest ◽  
Discrete Wavelet ◽  
Efficient Design ◽  
Pipeline Architecture ◽  
Wallace Tree ◽  
Vedic Multiplier ◽  
Reconstruction Image ◽  
Wallace Tree Multiplier

<span lang="EN-US">In digital image processing, the compression mechanism is utilized to enhance the visual perception and storage cost. By using hardware architectures, reconstruction of medical images especially Region of interest (ROI) part using Lossy image compression is a challenging task. In this paper, the ROI Based Discrete wavelet transformation (DWT) using separate Wallace- tree multiplier (WM) and modified Vedic Multiplier (VM) methods are designed. The Lifting based DWT method is used for the ROI compression and reconstruction. The 9/7 filter coefficients are multiplied in DWT using Wallace- tree multiplier (WM) and modified Vedic Multiplier (VM). The designed Wallace tree multiplier works with the parallel mechanism using pipeline architecture results with optimized hardware resources, and 8x8 Vedic multiplier designs improves the ROI reconstruction image quality and fast computation. To evaluate the performance metrics between ROI Based DWT-WM and DWT-VM on FPGA platform, The PSNR and MSE are calculated for different Brain MRI images, and also hardware constraints include Area, Delay, maximum operating frequency and power results are tabulated. The proposed model is designed using Xilinx platform using Verilog-HDL and simulated using ModelSim and Implemented on Artix-7 FPGA device.</span>

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata

2020 ◽  
Author(s):  
A. Arunkumar Gudivada ◽  
K. Jayaram Kumar ◽  
Srinivasa Rao Jajula ◽  
Durga Prasad Siddani ◽  
Praveen Kumar Poola ◽  
...  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Speed ◽  
Quantum Dot Cellular Automata ◽  
Wallace Tree ◽  
Wallace Tree Multiplier ◽  
Area Efficient
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