scholarly journals Power-Estimation for On-Chip VLSI Distributed RLC Global Interconnect Using Model Order Reduction Technique

2010 ◽  
Vol 1 (14) ◽  
pp. 96-101 ◽  
Author(s):  
Rajib Kar ◽  
Vikas Maheshwari ◽  
Md. Maqbool ◽  
Ashis K. Mal ◽  
A.K. Bhattacharjee
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