Power-Estimation for On-Chip VLSI Distributed RLC Global Interconnect Using Model Order Reduction Technique
2010 ◽
Vol 1
(14)
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pp. 96-101
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2012 ◽
Vol 6
(3)
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pp. 169-181
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2018 ◽
Vol 3
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pp. 140-148
2015 ◽
Vol 32
(3)
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pp. 767-779
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2016 ◽
Vol 28
(1)
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pp. 68-77
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