A Novel Power Estimation Method for On-chip VLSI Distributed RLCG Global Interconnects Using Model Order Reduction Technique

2010 ◽  
Author(s):  
Rajib Kar ◽  
V. Maheshwari ◽  
Sangeeta Mondal ◽  
Md. Maqbool ◽  
A.K. Mal ◽  
...  
Keyword(s):  
Model Order Reduction ◽  
Estimation Method ◽  
Order Reduction ◽  
Power Estimation ◽  
Reduction Technique ◽  
Model Order ◽  
Global Interconnects ◽  
On Chip

scholarly journals Power-Estimation for On-Chip VLSI Distributed RLC Global Interconnect Using Model Order Reduction Technique

2010 ◽  
Vol 1 (14) ◽  
pp. 96-101 ◽  
Author(s):  
Rajib Kar ◽  
Vikas Maheshwari ◽  
Md. Maqbool ◽  
Ashis K. Mal ◽  
A.K. Bhattacharjee
Keyword(s):  
Model Order Reduction ◽  
Order Reduction ◽  
Power Estimation ◽  
Reduction Technique ◽  
Model Order ◽  
Global Interconnect ◽  
On Chip
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