FPGA Implementation of an Approximate Booth-Wallace Tree Multiplier

2021 ◽  
Author(s):  
TALHA BIN ASLAM ◽  
Farhan Ahmed
Keyword(s):  
Fpga Implementation ◽  
Wallace Tree ◽  
Wallace Tree Multiplier

scholarly journals FPGA Implementation of 8-Bit Vedic Multiplier for DIT-FFT Application Using Urdhva Tiryagbhyam Sutra

2021 ◽  
pp. 156-165
Author(s):  
Rohith S ◽  
Kasetty Ram Babu ◽  
Chandrashekar M N
Keyword(s):  
Software Tool ◽  
Fpga Implementation ◽  
Verilog Hdl ◽  
Booth Multiplier ◽  
Wallace Tree ◽  
Vedic Multiplier ◽  
Array Multiplier ◽  
Wallace Tree Multiplier

This paper discusses FPGA Implementation of 8-Bit Vedic Multiplier and DIT-FFT Application Using Urdhva Tiryagbhyam Sutra. Initially 8-bit Vedic multiplier performance is compared with existing multiplier such as i) Wallace tree multiplier ii) Array multiplier iii) Booth multiplier. In this work Urdhva Tiryagbhyam (upright and across) Vedic sutra is used for multiplier design which provides better performance and consumes smaller time for computation. In this work, Modified Carry Save Adder (MCSA) is used to compute the sum of partially generated products. Further the multiplier is It reduces the computational delay towards the addition of unfinished products. The proposed design uses the Verilog HDL to develop the algorithm. The XILINX 14.7 software tool is used to simulate and synthesize the code. The proposed design is used for DIT FFT application.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata

2020 ◽  
Author(s):  
A. Arunkumar Gudivada ◽  
K. Jayaram Kumar ◽  
Srinivasa Rao Jajula ◽  
Durga Prasad Siddani ◽  
Praveen Kumar Poola ◽  
...  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Speed ◽  
Quantum Dot Cellular Automata ◽  
Wallace Tree ◽  
Wallace Tree Multiplier ◽  
Area Efficient

scholarly journals VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

2021 ◽  
Vol 14 (1) ◽  
pp. 22-31
Author(s):  
Kommalapati Monica ◽  
◽  
Dereddy Anuradha ◽  
Syed Rasheed ◽  
Barnala Shereesha ◽  
...  
Keyword(s):  
Power Consumption ◽  
Field Programmable Gate Array ◽  
Finite Impulse Response ◽  
Research Work ◽  
Industrial Applications ◽  
Booth Multiplier ◽  
Wallace Tree ◽  
Look Up Table ◽  
Field Programmable ◽  
Wallace Tree Multiplier

Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

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