scholarly journals FPGA Implementation of Convolutional Encoder And Hard Decision Viterbi Decoder

2016 ◽  
pp. 126-130
Author(s):  
J. Tulasi ◽  
T.Venkata Lakshmi ◽  
M. Kamaraju
Keyword(s):  
Communication Systems ◽  
Block Codes ◽  
Viterbi Decoder ◽  
Space Communications ◽  
Convolutional Coding ◽  
Coding Scheme ◽  
Alternative Approach ◽  
Constraint Length ◽  
Convolutional Encoder ◽  
Digital Communication Systems

In this paper, we concern with designing and implementing a convolutional encoder and Viterbi decoder which are the essential block in digital communication systems using FPGA technology. Convolutional coding is a coding scheme used in communication systems including deep space communications and wireless communications. It provides an alternative approach to block codes for transmission over a noisy channel. The block codes can be applied only for the block of data. The convolutional coding has an advantage over the block codes in that it can be applied to a continuous data stream as well as to blocks of data.The motivation of this paper is to realize a Viterbi decoder having Constraint length 9 and code rate 1/2 by Xilinx 12.4i tools.

scholarly journals RESEARCH OF CHARACTERISTICS OF NOISE IMMUNITY WITH USE OF ORTHOGONAL CODING

2018 ◽  
pp. 80-85 ◽  
Author(s):  
A. V. Rabin ◽  
M. A. Dobroselskij ◽  
V. A. Lipatnikov
Keyword(s):  
Fading Channels ◽  
Communication Systems ◽  
Signal To Noise Ratio ◽  
Additive White Gaussian Noise ◽  
Digital Signals ◽  
Coding Gain ◽  
Convolutional Coding ◽  
Orthogonal Codes ◽  
Effective Use ◽  
Digital Communication Systems

In the digital communication systems for noise immunity's increase with the fixed code rate it is proposed to use an additional orthogonal coding developed by the authors. It is an analogue of convolutional coding over the rational numbers' field. Transmission of digital signals in Additive white Gaussian noise (AWGN) channel and fading channels is considered including a joint use of the orthogonal and correcting codes (block and convolutional). It is shown that losses in signal-to-noise ratio can be significantly reduced by use of orthogonal coding. By increase of matrices' order, on which basis orthogonal codes are constructed, the coding gain grows also. By use of the proposed by the authors orthogonal coding the required quality of communication is implemented with a smaller energy cost. The significant coding gain (up to 6,4 dB in the channels with the AWGN, up to 22,74 dB in the fading channels) provided by more effective use of energy of transmitted signals is reached without increase in complexity and cost of transmitting/receiving devices.

scholarly journals Verilog based efficient convolution encoder and viterbi decoder

2019 ◽  
Vol 8 (1) ◽  
pp. 75
Author(s):  
Md. Abdul Rawoof ◽  
Umasankar Ch. ◽  
D. Naresh Kumar ◽  
D. Khalandar Basha ◽  
N. Madhur
Keyword(s):  
Error Correction ◽  
Communication Systems ◽  
Viterbi Algorithm ◽  
Data Communication ◽  
Vital Role ◽  
Redundant Information ◽  
Viterbi Decoder ◽  
Correction Technique ◽  
Source Data ◽  
Digital Communication Systems

In the<strong><em> </em></strong>today’s<strong><em> </em></strong>digital communication Systems,<strong><em> </em></strong>transmission of data with more reliability and efficiency is the most challenging issue for data communication through channels. In communication systems, error correction technique plays a vital role. In error correction techniques, The capacity of data can be enhanced by adding the redundant information for the source data while transmitting the data through channel. It mainly focuses on the awareness of convolution encoder and Viterbi decoder. For decoding convolution codes Viterbi algorithm is preferred.

scholarly journals A HARDWARE IMPLEMENTATION OF PUNGURED CONVOLUTIONAL CODES TO COMPLETE A VITERBI DECODER CORE

2005 ◽  
Vol 3 (02) ◽  
Author(s):  
E. Garda ◽  
M. Guzmán ◽  
D. Torres
Keyword(s):  
Large Scale ◽  
Convolutional Codes ◽  
Viterbi Decoder ◽  
Single Chip ◽  
Description Language ◽  
Large Scale Integration ◽  
Constraint Length ◽  
Hardware Description ◽  
Scale Integration ◽  
Convolutional Encoder

This paper presents a VLSI (Very Large Scale Integration) implementation of high punctured convolutional codes.We present a new circuit architecture that is capable of processing up to 10 convolutional codes rate (n-1)/n withthe constraint length-7 derived by the puncturing technique from the basic rate-1/2. The present circuit wasdesigned in order to complete an existing Viterbi decoder core, adding some extra functionality such as aconvolutional encoder, differential encoder/decoder, punctured convolutional encoder and symbol insertion todepuncture the received data. This extra functionality includes 10 different programmable coding rates without theneed to add additional logic in the system implementation, while other existing coders need it to attain highercoding rates. Therefore, a single chip solution is presented. The design was implemented in VHDL (Very High SpeedIntegrated Circuit Hardware Description Language) synthesized in Synopsys tool, and tested in a FPGA. Functionalverification was done, by means of simulation, to ensure that the circuit implements intended functionality. Suchsimulations were executed using Synopsys and a Sun Ultra Sparc 10 workstation. Different bit error probabilityperformance curves show an agreement between simulated and theoretical values.

Design of ACS Architecture Using FinFET and CNTFET Devices for Low-Power Viterbi Decoder Using Asynchronous Techniques for Digital Communication Systems

2021 ◽  
Author(s):  
A Bernard Rayappa ◽  
TVP Sundararajan
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
Viterbi Algorithm ◽  
Model Performance ◽  
Cmos Technology ◽  
High Rate ◽  
Viterbi Decoder ◽  
Hardware Complexity ◽  
Large Power ◽  
Constraint Length

Viterbi algorithm is the most popular algorithm used to decode the convolution code, but its computational complexity increases exponentially with the increasing constraint length due to a large number of Trellis transitions. However, high constraint length is necessary to improve the accuracy of the decoding process for the high rate convolution code. In particular, the Add-Compare-Select (ACS) module of the Viterbi Decoder will have large numbers of trellis states and trellis transitions with increased constraint lengths, which give rise to high hardware complexity and large power consumption. As the performance of the Viterbi decoder mainly depends on its efficient implementation of the ACS module, in the literature, several methods are presented for the implementation of ACS for the Viterbi decoder. The methods based on Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer, Shannon’s decomposition circuits, body-biased pseudo-NMOS logic and Quasi Delay Insensitive (QDI) timing model performance is analyzed. The methods are implemented using CMOS technology. In this paper, FinFET and CNTFET-based ACS implementation is performed. From the analysis, it has been found that the Carbon Nanotube-based implementation is better in performance when compared to the CMOS and FinFET technology. The proposed QDI model and retiming circuits for ACS block operate above 1[Formula: see text]GHz with high driving current and low power.

scholarly journals Implementation of a standard inner convolutional codec for DVB-T system using VHDL

2017 ◽  
Vol 6 (4) ◽  
pp. 131
Author(s):  
Dina M. Hussein ◽  
Abdelhalim Zekry ◽  
Said Baioumy ◽  
Fatma El-Newagy
Keyword(s):  
Channel Coding ◽  
Communication Systems ◽  
Forward Error Correction ◽  
Vital Role ◽  
Viterbi Decoder ◽  
Error Protection ◽  
Digital Terrestrial Television ◽  
Forward Error ◽  
Convolutional Encoder ◽  
T System

Forward error correction (FEC) plays a vital role in digital communication systems. DVB-T system uses FEC as a channel coding technique to restore any data lost through transmission to the receiver. DVB-T system uses two levels of error protection. The first level is applied in the data transmitted by using a Reed-Solomon RS (204, 188) code followed by a convolutional interleaver. The other level of error protection is a punctured convolutional inner coding followed by an inner interleave in which the data sequence is rearranged again to minimize the influence of burst errors.This paper describes the implementation of inner convolutional codec (Convolutional coder and Viterbi Decoder) and inner de/interleaving of a standard DVB-T system with a constrained length of 7 and a code rate of 2/3 using VHDL on virtex-6 FPGA xc6vlx240t. The designed channel convolutional encoder and Viterbi decoder follow European Standard ETSI EN 300 744 for digital terrestrial television. Verification of the design is accomplished by loop back and by comparison with the corresponding Xilinx core. Utilization and timing re-ports of the implemented device on Vertex 6 are included.

Viterbi Decoder Design of Beidou RDSS Receiver

2013 ◽  
Vol 431 ◽  
pp. 331-335
Author(s):  
Xiao Hu Yu
Keyword(s):  
Channel Coding ◽  
Optimized Design ◽  
Receiver Design ◽  
Viterbi Decoder ◽  
Hardware Complexity ◽  
Coding Scheme ◽  
Constraint Length ◽  
Decoder Design ◽  
Convolutional Encoding

Firstly, the convolutional encoding with constraint length of 7 is used as the channel coding scheme in Beidou RDSS system. In addition, in receiver design Viterbi Decoder serves as the decoder of convolutional encoding. Finally, the optimized design of hardware construction in traditional Viterbi compared with that in decoder is introduced to reduce hardware complexity.

scholarly journals Practical understanding of the operating principle of digital communication systems

2019 ◽  
Vol 16 (1) ◽  
pp. 299 ◽  
Author(s):  
Gebrehiwet Gebrekrstos Lema ◽  
Teklehaymanot Baweke Reda ◽  
Dawit Hailu ◽  
Tole Sutikno
Keyword(s):  
Communication System ◽  
Channel Coding ◽  
Communication Systems ◽  
Digital Communication ◽  
Operating Principle ◽  
Binary Channel ◽  
Band Pass ◽  
Digital Communication System ◽  
Convolutional Encoder ◽  
Digital Communication Systems

There are many students and researcher who doesn’t really understand the practical operating principle of digital communication system. Hence in this paper, the digital communication system is studied and simulated. In the system kit development text and audio inputs are taken and encrypted with different encryption techniques including additive cipher, multiplicative cipher and affine ciphers. The encrypted data is converted in to an 8-bit binary, channel encoded with distinct channel coding styles like linear block encoder, cyclic encoder and convolutional encoder, line coded and band pass modulated by different digital modulation techniques. Finally, the developed software is tested with equivalent inputs of the current national TV broadcasting and the results found are correct according to the theoretical analysis of the discussion.

Security Analysis of Wireless Authentication Protocols

2019 ◽  
Vol 9 (2) ◽  
pp. 247-252 ◽  
Author(s):  
Ashish Joshi ◽  
Amar Kumar Mohapatra
Keyword(s):  
Execution Time ◽  
Communication Systems ◽  
Security Analysis ◽  
Cryptographic Protocols ◽  
Command Line ◽  
Time Analysis ◽  
Authentication Protocols ◽  
Replay Attack ◽  
Peer Communication ◽  
Digital Communication Systems

Background & Objective: Cryptographic protocols had been evident method for ensuring con dentiality, Integrity and authentication in various digital communication systems. However the validation and analysis of such cryptographic protocols was limited to usage of formal mathematical models until few years back. Methods: In this paper, various popular cryptographic protocols have been studied. Some of these protocols (PAP, CHAP, and EAP) achieve security goals in peer to peer communication while others (RADIUS, DIAMETER and Kerberos) can work in multiparty environment. These protocols were validated and analysed over two popular security validation and analysis tools AVISPA and Scyther. The protocols were written according to their documentation using the HLPSL and SPDL for analysis over AVISPA and Scyther respectively. The results of these tools were analysed to nd the possible attack an each protocol. Afterwards The execution time analysis of the protocols were done by repeating the experiment for multiple iterations over the command line versions of these tools.As the literature review suggested, this research also validates that using password based protocols (PAP) is faster in terms of execution time as compared to other methods, Usage of nonces tackles the replay attack and DIAMETER is secure than RADIUS. Results and Conclusion: The results also showed us that DIAMETER is faster than RADIUS. Though Kerberos protocol was found to safe, the results tell us that it is compromisable under particular circumstances.

Sign in / Sign up

Export Citation Format

Share Document