scholarly journals THE EFFECT OF DATA-REUSE TRANSFORMATIONS ON MULTIMEDIA APPLICATIONS FOR APPLICATION SPECIFIC PROCESSORS

2014 ◽  
pp. 102-109
Author(s):  
N. Vassiliadis ◽  
A. Chormoviti ◽  
N. Kavvadias ◽  
S. Nikolaidis
Keyword(s):  
Energy Consumption ◽  
Power Consumption ◽  
Multimedia Applications ◽  
Data Reuse ◽  
Instruction Set ◽  
Specific Instruction ◽  
Data Transfers ◽  
And Performance ◽  
And Storage ◽  
Application Specific

Multimedia applications are characterized by a high number of data transfers and storage operations. Appropriate transformations can be applied at the algorithmic level to improve crucial implementation characteristics. In this paper, the effect of data-reuse transformations on power consumption and performance of multimedia applications, realized on an Application Specific Instruction set Processor (ASIP), is examined. An ASIP for multimedia applications designed based on a complete methodology is used to evaluate this effect. Results prove the efficiency of the ASIP solution and indicate benefits from the use of the data-reuse transformations in terms of energy consumption and performance. Also, preliminary results from the exploitation of instruction buffering technique to reduce the energy consumption of the ASIP are presented.

Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier

2019 ◽  
Vol 13 (2) ◽  
pp. 174-180
Author(s):  
Poonam Sharma ◽  
Ashwani Kumar Dubey ◽  
Ayush Goyal
Keyword(s):  
Image Processing ◽  
High Speed ◽  
Computation Time ◽  
Digital Signal ◽  
Instruction Set ◽  
Computationally Efficient ◽  
Specific Instruction ◽  
Processor Core ◽  
Speed Performance ◽  
Application Specific

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.

scholarly journals Power and Performance Evaluation of Memory-Intensive Applications

Energies ◽  
2021 ◽  
Vol 14 (14) ◽  
pp. 4089
Author(s):  
Kaiqiang Zhang ◽  
Dongyang Ou ◽  
Congfeng Jiang ◽  
Yeliang Qiu ◽  
Longchuan Yan
Keyword(s):  
Energy Efficiency ◽  
Energy Consumption ◽  
Power Consumption ◽  
Job Scheduling ◽  
Memory System ◽  
Processor Core ◽  
Memory Efficiency ◽  
And Performance ◽  
Reasonable Use ◽  
Server System

In terms of power and energy consumption, DRAMs play a key role in a modern server system as well as processors. Although power-aware scheduling is based on the proportion of energy between DRAM and other components, when running memory-intensive applications, the energy consumption of the whole server system will be significantly affected by the non-energy proportion of DRAM. Furthermore, modern servers usually use NUMA architecture to replace the original SMP architecture to increase its memory bandwidth. It is of great significance to study the energy efficiency of these two different memory architectures. Therefore, in order to explore the power consumption characteristics of servers under memory-intensive workload, this paper evaluates the power consumption and performance of memory-intensive applications in different generations of real rack servers. Through analysis, we find that: (1) Workload intensity and concurrent execution threads affects server power consumption, but a fully utilized memory system may not necessarily bring good energy efficiency indicators. (2) Even if the memory system is not fully utilized, the memory capacity of each processor core has a significant impact on application performance and server power consumption. (3) When running memory-intensive applications, memory utilization is not always a good indicator of server power consumption. (4) The reasonable use of the NUMA architecture will improve the memory energy efficiency significantly. The experimental results show that reasonable use of NUMA architecture can improve memory efficiency by 16% compared with SMP architecture, while unreasonable use of NUMA architecture reduces memory efficiency by 13%. The findings we present in this paper provide useful insights and guidance for system designers and data center operators to help them in energy-efficiency-aware job scheduling and energy conservation.

Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors

2017 ◽  
Vol 66 (4) ◽  
pp. 647-660 ◽  
Author(s):  
Tuo Li ◽  
Muhammad Shafique ◽  
Jude Angelo Ambrose ◽  
Jorg Henkel ◽  
Sri Parameswaran
Keyword(s):  
Instruction Set ◽  
Specific Instruction ◽  
Fine Grained ◽  
Checkpoint Recovery ◽  
Instruction Set Processors ◽  
Application Specific
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