An analytical model for the power consumption of Dual‐Mode EEE

2016 ◽  
Vol 52 (15) ◽  
pp. 1308-1310 ◽  
Author(s):  
M. Mostowfi ◽  
K. Shafie
Keyword(s):  
Power Consumption ◽  
Analytical Model ◽  
Dual Mode

scholarly journals Sharp Skirt Dual-Mode Bandpass Filter with Overlay Plate to Control Upper Passband Edge

2019 ◽  
Vol 8 (6) ◽  
pp. 2357-2360
Keyword(s):  
Analytical Model ◽  
Insertion Loss ◽  
Return Loss ◽  
Bandpass Filter ◽  
Center Frequency ◽  
Dual Mode ◽  
Rf Receivers ◽  
Attenuation Level ◽  
Frequency Selective ◽  
Fixed Center

This paper presents design and analytical model for Sharp Skirt Dual-Mode Bandpass Filter for RF receivers. Proposed filter is designed using open stub loaded H shaped resonator. Based on analytical model insertion loss S21 and return loss S11 for proposed filter are demonstrated. Inductive Overlaying plate is proposed to control upper passband edge of proposed filter to improve frequency selectivity with fixed center frequency. The proposed filter has sharp frequency selective range from 5.1GHz to 9.2GHz. With overlay plate, frequency selective range is tuned to 5.1GHz-8.6GHz. Without overlaying plate the proposed filter has return loss greater than 10dB and insertion loss of 0.7dB. Lower and upper passband edges are at 5.1GHz and 9.2GHz with attenuation level of 52dB and 54dB respectively. With overlaying plate, the filter has same S 11 and S 21 parameters, but upper passband edge is shifted from 9.2GHz to 8.6GHz

A Dual-Mode Microwave Applicator for Liver Tumor Thermotherapy

Frequenz ◽  
2018 ◽  
Vol 72 (3-4) ◽  
pp. 141-149 ◽  
Author(s):  
Carolin Reimann ◽  
Martin Schüßler ◽  
Rolf Jakoby ◽  
Babak Bazrafshan ◽  
Frank Hübner ◽  
...  
Keyword(s):  
Power Consumption ◽  
Liver Tumor ◽  
Thermal Ablation ◽  
Multimodal Imaging ◽  
Microwave Ablation ◽  
Dielectric Analysis ◽  
Frequency Range ◽  
Dual Mode ◽  
Microwave Applicator ◽  
5 Ghz

Abstract The concept of a novel dual-mode microwave applicator for diagnosis and thermal ablation treatment of tumorous tissue is presented in this paper. This approach is realized by integrating a planar resonator array to, firstly, detect abnormalities by a relative dielectric analysis, and secondly, perform a highly localized thermal ablation. A further essential advantage is addressed by designing the applicator to be MRI compatible to provide a multimodal imaging procedure. Investigations for an appropriate frequency range lead to the use of much higher operating frequencies between 5 GHz and 10 GHz, providing a significantly lower power consumption for microwave ablation of only 20 W compared to commercial available applicators.

scholarly journals Ten-Bit 0.909-MHz 8-Channel Dual-Mode Successive Approximation ADC for a BLDC Motor Drive

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 830
Author(s):  
Chong-Cheng Huang ◽  
Guo-Ming Sung ◽  
Xiong Xiao ◽  
Shan-Hao Sung ◽  
Chao-Hung Huang
Keyword(s):  
Power Consumption ◽  
Successive Approximation ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Motor Drive ◽  
Cmos Process ◽  
Bldc Motor ◽  
Signal To Noise ◽  
Dual Mode ◽  
Successive Approximation Adc

This paper presents a 10-bit 0.909-MHz 8-channel dual-mode successive approximation (SAR) analogue-to-digital converter (ADC) for brushless direct current (BLDC) motor drive, using a Taiwan Semiconductor Manufacturing (TSMC) 0.25 μm 1P3M Complementary Metal Oxide Semiconductor (CMOS) process. The sample-and-hold (S/H) circuit operates with two sampling modes. One is individually sampling eight channels in sequence with an S/H circuit and the other is sampling four channels simultaneously with four S/H circuits. All sampled data will be digitized with high-speed SAR ADC in time division multiplexing (TDM). A dynamic latch-type comparator is utilized to latch the output at an upper or lower level. The advantage of the designed comparator is that it performs with positive feedback to quickly complete the latch function. The double-tail latch-type architecture is utilized to mitigate the significant kickback effect by separating the pre-amplifier stage from the latch. By integrating an input NMOSFET with an input PMOSFET, the designed latch-type comparator can perform with full-swing input voltage. Measurements show that the signal-to-noise ratio (SNR), signal-to-noise-and-distortion ratio (SNDR), effective number of bits (ENOB), power consumption, and chip area are 50.56 dB, 57.03 dB, 8.11 bits, 833 μW, and 1.35 × 0.98 mm2, respectively. The main advantages of the proposed multichannel dual-mode SAR ADC are its low power consumption of 833 μW and high measured resolution of 8.11 bits.

scholarly journals POWER-CONSUMPTION-ORIENTED CHECKABILITY FOR FPGA-BASED COMPONENTS OF SAFETY-RELATED SYSTEMS

2019 ◽  
pp. 118-126
Author(s):  
Oleksandr Drozd ◽  
Viktor Antoniuk ◽  
Miroslav Drozd ◽  
Volodymyr Karpinskyi ◽  
Pavlo Bykovyy
Keyword(s):  
Power Consumption ◽  
Fault Tolerant ◽  
Logical Form ◽  
Control Object ◽  
Fpga Implementation ◽  
Dual Mode ◽  
Increased Risk ◽  
Input Signals ◽  
Analytical Assessment ◽  
The Common

This paper is dedicated to the problem of the circuit checkability of components in the safety-related systems, which operate objects of the increased risk and are aimed at ensuring safety of both a system and a control object for accident prevention and a decrease in their consequences. Importance of the checkability of the circuits for ensuring safety in critical applications is emphasized as safety is based on the use of fault tolerant circuitry decisions and their efficiency is defined by the circuit checkability. Development of a logical checkability from testability to structurally functional and dual-mode model which formalizes a problem of the hidden faults and defines ways of its solution is shown. The limitation of a logical checkability in detection of faults in chains of the common signals and the need for development of checkability out of the limits of a logical form, including suitability to checking the circuits on the basis of their power consumption is considered. Power-consumption-oriented checkability (Power-checkability) allowing detection of faults in chains of the common signals is defined. Its analytical assessment for the circuits implemented in FPGA is offered. Experiments providing estimation of power-checkability for FPGA-implementation of iterative array multipliers with various activities of input signals are carried out.

scholarly journals Randomized routing of virtual machines in IaaS data centers

2019 ◽  
Vol 5 ◽  
pp. e211
Author(s):  
Hadi Khani ◽  
Hamed Khanmirza
Keyword(s):  
Cloud Computing ◽  
Quality Of Service ◽  
Power Consumption ◽  
Analytical Model ◽  
Data Center ◽  
Large Scale ◽  
Data Centers ◽  
Virtual Machines ◽  
General Distribution

Cloud computing technology has been a game changer in recent years. Cloud computing providers promise cost-effective and on-demand resource computing for their users. Cloud computing providers are running the workloads of users as virtual machines (VMs) in a large-scale data center consisting a few thousands physical servers. Cloud data centers face highly dynamic workloads varying over time and many short tasks that demand quick resource management decisions. These data centers are large scale and the behavior of workload is unpredictable. The incoming VM must be assigned onto the proper physical machine (PM) in order to keep a balance between power consumption and quality of service. The scale and agility of cloud computing data centers are unprecedented so the previous approaches are fruitless. We suggest an analytical model for cloud computing data centers when the number of PMs in the data center is large. In particular, we focus on the assignment of VM onto PMs regardless of their current load. For exponential VM arrival with general distribution sojourn time, the mean power consumption is calculated. Then, we show the minimum power consumption under quality of service constraint will be achieved with randomize assignment of incoming VMs onto PMs. Extensive simulation supports the validity of our analytical model.

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