scholarly journals Open and Short Stubs Employing the Periodically Arrayed Grounded-strip Structure on the Silicon Substrate and Their Application to Miniaturized RF Filters on the Silicon RFIC

2016 ◽  
Vol 17 (4) ◽  
pp. 217-221
Author(s):  
Young Yun
Keyword(s):  
Silicon Substrate ◽  
Rf Filters ◽  
Strip Structure

InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate

2014 ◽  
Vol E97.C (7) ◽  
pp. 677-682
Author(s):  
Sung YUN WOO ◽  
Young JUN YOON ◽  
Jae HWA SEO ◽  
Gwan MIN YOO ◽  
Seongjae CHO ◽  
...  
Keyword(s):  
Silicon Substrate ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Transistor

Transport Properties Of Metallic Nanowires On Silicon Substrate

2014 ◽  
Vol 2 (1) ◽  
pp. 20-23
Author(s):  
Jaskiran Kaur ◽  
◽  
Surinder Singh ◽  
Keyword(s):  
Transport Properties ◽  
Silicon Substrate ◽  
Metallic Nanowires

Process Induced Defects in the Silicon Substrate: Approaches for Successful Failure Analysis

2010 ◽  
Author(s):  
J.G. van Hassel ◽  
Xiao-Mei Zhang
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Silicon Substrate ◽  
Processing Technique ◽  
Electrical Characteristics ◽  
Localization Method ◽  
The Right ◽  
Induced Defects

Abstract Failures induced in the silicon substrate by process marginalities or process mistakes need continuous attention in new as well as established technologies. Several case studies showing implant related defects and dislocations in silicon will be discussed. Depending on the electrical characteristics of the failure the localization method has to be chosen. The emphasis of the discussion will be on the importance of the right choice for further physical de-processing to reveal the defect. This paper focuses on the localization method, the de- processing technique and the use of Wright etch for subsequent TEM preparation.

Studies on a Novel Qualification Method of Silicon Nitride Layer

2016 ◽  
Author(s):  
Younan Hua ◽  
Bingsheng Khoo ◽  
Henry Leong ◽  
Yixin Chen ◽  
Eason Chan ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Silicon Substrate ◽  
Nitride Layer ◽  
Passivation Layer ◽  
Wafer Fabrication ◽  
Wafer Surface ◽  
Si3n4 Layer ◽  
Silicon Nitride Layer ◽  
Passivation Layers ◽  
Pinhole Test

Abstract In wafer fabrication, a silicon nitride (Si3N4) layer is widely used as passivation layer. To qualify the passivation layers, traditionally chemical recipe PAE (H3PO4+ HNO3) is used to conduct passivation pinhole test. However, it is very challenging for us to identify any pinholes in the Si3N4 layer with different layers underneath. For example, in this study, the wafer surface is Si3N4 layer and the underneath layer is silicon substrate. The traditional receipt of PAE cannot be used for passivation qualification. In this paper, we will report a new recipe using KOH solution to identify the pinhole in the Si3N4 passivation layer.

DNA Hybridization on Chitosan-Functionalized Silicon Substrate

2016 ◽  
Vol 12 (5) ◽  
pp. 464-471 ◽  
Author(s):  
Amina Omar ◽  
El-Sayed M. El-Sayed ◽  
Mona S. Talaat ◽  
Medhat Ibrahim
Keyword(s):  
Silicon Substrate ◽  
Dna Hybridization

scholarly journals Author Correction: Photodetection Characteristics of Gold Coated AFM Tips and n-Silicon Substrate nano-Schottky Interfaces

2020 ◽  
Vol 10 (1) ◽  
Author(s):  
Yawar Abbas ◽  
Ayman Rezk ◽  
Fatmah Alkindi ◽  
Irfan Saadat ◽  
Ammar Nayfeh ◽  
...  
Keyword(s):  
Silicon Substrate ◽  
Afm Tips

An amendment to this paper has been published and can be accessed via a link at the top of the paper.

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