A Fault-Tolerant Processor Core Architecture for Safety-Critical Automotive Applications

Cyber-physical systems (CPSs) are co-engineered integrating with physical and computational components networks. Additionally, a CPS is a mechanism controlled or monitored by computer-based algorithms, tightly interacting with the internet and its users. This chapter presents the definitions relating to dependability, safety-critical and fault-tolerance of CPSs. These definitions are supplemented by other definitions like reliability, availability, safety, maintainability, integrity. Threats to dependability and security like faults, errors, failures are also discussed. Taxonomy of different faults and attacks in CPSs are also presented in this chapter. The main objective of this chapter is to give the general information about secure CPS to the learners for the further enhancement in the field of CPSs.

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High-Power-Density Fault-Tolerant PM Generator for Safety-Critical Applications

IEEE Transactions on Industry Applications ◽

10.1109/tia.2013.2282852 ◽

2014 ◽

Vol 50 (3) ◽

pp. 1717-1728 ◽

Cited By ~ 19

Author(s):

Ayman M. EL-Refaie ◽

Manoj R. Shah ◽

Kum-Kang Huh

Keyword(s):

Power Density ◽

High Power ◽

Fault Tolerant ◽

High Power Density ◽

Safety Critical

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Low Cost Fault Tolerant and Redundant Multiplex Wiring System for Automotive Applications

10.4271/2004-01-1572 ◽

2004 ◽

Author(s):

Kelvin Shih

Keyword(s):

Fault Tolerant ◽

Low Cost ◽

Automotive Applications ◽

Wiring System

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Architecture and Design of a Spiking Neuron Processor Core Towards the Design of a Large-scale Event-Driven 3D-NoC-based Neuromorphic Processor

SHS Web of Conferences ◽

10.1051/shsconf/20207704003 ◽

2020 ◽

Vol 77 ◽

pp. 04003

Author(s):

Mark Ogbodo ◽

Khanh Dang ◽

Fukuchi Tomohide ◽

Abderazek Abdallah

Keyword(s):

Low Power ◽

Large Scale ◽

Fault Tolerant ◽

Three Dimensional ◽

Spiking Neuron ◽

Chip Area ◽

Processor Core ◽

Neuromorphic Systems ◽

Event Driven ◽

On Chip

Neuromorphic computing tries to model in hardware the biological brain which is adept at operating in a rapid, real-time, parallel, low power, adaptive and fault-tolerant manner within a volume of 2 liters. Leveraging the event driven nature of Spiking Neural Network (SNN), neuromorphic systems have been able to demonstrate low power consumption by power gating sections of the network not driven by an event at any point in time. However, further exploration in this field towards the building of edge application friendly agents and efficient scalable neuromorphic systems with large number of synapses necessitates the building of small-sized low power spiking neuron processor core with efficient neuro-coding scheme and fault tolerance. This paper presents a spiking neuron processor core suitable for an event-driven Three-Dimensional Network on Chip (3D-NoC) SNN based neuromorphic systems. The spiking neuron Processor core houses an array of leaky integrate and fire (LIF) neurons, and utilizes a crossbar memory in modelling the synapses, all within a chip area of 0.12mm2 and was able to achieves an accuracy of 95.15% on MNIST dataset inference.

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