Using TLA+ in the Development of a Safety-Critical Fault-Tolerant Middleware

2017 ◽  
Author(s):  
Stefan Resch ◽  
Michael Paulitsch
Keyword(s):  
Fault Tolerant ◽  
Safety Critical ◽  
Critical Fault

Safety-Critical, Dependable, and Fault-Tolerant Cyber-Physical Systems

2018 ◽  
pp. 54-78
Author(s):  
Guru Prasad Bhandari ◽  
Ratneshwer Gupta
Keyword(s):  
Fault Tolerance ◽  
Fault Tolerant ◽  
Cyber Physical Systems ◽  
General Information ◽  
The Internet ◽  
Physical Systems ◽  
Safety Critical ◽  
Computer Based

Cyber-physical systems (CPSs) are co-engineered integrating with physical and computational components networks. Additionally, a CPS is a mechanism controlled or monitored by computer-based algorithms, tightly interacting with the internet and its users. This chapter presents the definitions relating to dependability, safety-critical and fault-tolerance of CPSs. These definitions are supplemented by other definitions like reliability, availability, safety, maintainability, integrity. Threats to dependability and security like faults, errors, failures are also discussed. Taxonomy of different faults and attacks in CPSs are also presented in this chapter. The main objective of this chapter is to give the general information about secure CPS to the learners for the further enhancement in the field of CPSs.

High-Power-Density Fault-Tolerant PM Generator for Safety-Critical Applications

2014 ◽  
Vol 50 (3) ◽  
pp. 1717-1728 ◽  
Author(s):  
Ayman M. EL-Refaie ◽  
Manoj R. Shah ◽  
Kum-Kang Huh
Keyword(s):  
Power Density ◽  
High Power ◽  
Fault Tolerant ◽  
High Power Density ◽  
Safety Critical

A Fault-Tolerant Processor Core Architecture for Safety-Critical Automotive Applications

2005 ◽  
Author(s):  
Emmanuel Touloupis ◽  
James A Flint ◽  
Vassilios A Chouliaras ◽  
David D. Ward
Keyword(s):  
Fault Tolerant ◽  
Automotive Applications ◽  
Processor Core ◽  
Safety Critical

Optimizing Fault Tolerance for Multi-Processor System-on-Chip

2011 ◽  
pp. 66-91 ◽  
Author(s):  
Dimitar Nikolov ◽  
Mikael Väyrynen ◽  
Urban Ingelsson ◽  
Virendra Singh ◽  
Erik Larsson
Keyword(s):  
Fault Tolerance ◽  
Error Probability ◽  
Fault Tolerant ◽  
General Purpose ◽  
System On Chip ◽  
Probability Estimation ◽  
Communication Overhead ◽  
Mathematical Framework ◽  
Safety Critical ◽  
On Chip

While the rapid development in semiconductor technologies makes it possible to manufacture integrated circuits (ICs) with multiple processors, so called Multi-Processor System-on-Chip (MPSoC), ICs manufactured in recent semiconductor technologies are becoming increasingly susceptible to transient faults, which enforces fault tolerance. Work on fault tolerance has mainly focused on safety-critical applications; however, the development of semiconductor technologies makes fault tolerance also needed for general-purpose systems. Different from safety-critical systems where meeting hard deadlines is the main requirement, it is for general-purpose systems more important to minimize the average execution time (AET). The contribution of this chapter is two-fold. First, the authors present a mathematical framework for the analysis of AET. Their analysis of AET is performed for voting, rollback recovery with checkpointing (RRC), and the combination of RRC and voting (CRV) where for a given job and soft (transient) error probability, the authors define mathematical formulas for each of the fault-tolerant techniques with the objective to minimize AET while taking bus communication overhead into account. And, for a given number of processors and jobs, the authors define integer linear programming models that minimize AET including communication overhead. Second, as error probability is not known at design time and it can change during operation, they present two techniques, periodic probability estimation (PPE) and aperiodic probability estimation (APE), to estimate the error probability and adjust the fault tolerant scheme while the IC is in operation.

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