scholarly journals Reducing Power and Energy Consumption of Nonvolatile Microcontrollers with Transparent On-Chip Instruction Cache

2014 ◽  
Vol 05 (11) ◽  
pp. 253-264 ◽  
Author(s):  
Dahoo Kim ◽  
Itaru Hida ◽  
Eric Shun Fukuda ◽  
Tetsuya Asai ◽  
Masato Motomura
Keyword(s):  
Energy Consumption ◽  
Reducing Power ◽  
Instruction Cache ◽  
On Chip ◽  
Power And Energy

scholarly journals Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems

2011 ◽  
Vol 2011 ◽  
pp. 1-17 ◽  
Author(s):  
Diana Göhringer ◽  
Jonathan Obie ◽  
André L. S. Braga ◽  
Michael Hübner ◽  
Carlos H. Llanos ◽  
...  
Keyword(s):  
Energy Consumption ◽  
Multiprocessor Systems ◽  
Clock Frequency ◽  
Power Performance ◽  
Frequency Scaling ◽  
Specific System ◽  
Efficient System ◽  
System Solution ◽  
On Chip ◽  
Power And Energy

The design space of FPGA-based processor systems is huge, because many parameters can be modified at design- and runtime to achieve an efficient system solution in terms of performance, power and energy consumption. Such parameters are, for example, the number of processors and their configurations, the clock frequencies at design time, the use of dynamic frequency scaling at runtime, the application task distribution, and the FPGA type and size. The major contribution of this paper is the exploration of all these parameters and their impact on performance, power dissipation, and energy consumption for four different application scenarios. The goal is to introduce a first approach for a developer's guideline, supporting the choice of an optimized and specific system parameterization for a target application on FPGA-based multiprocessor systems-on-chip. The FPGAs used for these explorations were Xilinx Virtex-4 and Xilinx Virtex-5. The performance results were measured on the FPGA while the power consumption was estimated using the Xilinx XPower Analyzer tool. Finally, a novel runtime adaptive multiprocessor architecture for dynamic clock frequency scaling is introduced and used for the performance, power and energy consumption evaluations.

A case for shared instruction cache on chip multiprocessors running OLTP

2004 ◽  
Vol 32 (3) ◽  
pp. 11-18 ◽  
Author(s):  
Partha Kundu ◽  
Murali Annavaram ◽  
Trung Diep ◽  
John Shen
Keyword(s):  
Chip Multiprocessors ◽  
Instruction Cache ◽  
On Chip

scholarly journals Compiler-directed scratchpad memory data transfer optimization for multithreaded applications on a heterogeneous many-core architecture

2021 ◽  
Author(s):  
Xiaohan Tao ◽  
Jianmin Pang ◽  
Jinlong Xu ◽  
Yu Zhu
Keyword(s):  
Energy Consumption ◽  
High Performance ◽  
Scientific Computing ◽  
Data Transfer ◽  
Performance Model ◽  
Experimental Result ◽  
Transfer Model ◽  
Scratchpad Memory ◽  
On Chip ◽  
Many Core

AbstractThe heterogeneous many-core architecture plays an important role in the fields of high-performance computing and scientific computing. It uses accelerator cores with on-chip memories to improve performance and reduce energy consumption. Scratchpad memory (SPM) is a kind of fast on-chip memory with lower energy consumption compared with a hardware cache. However, data transfer between SPM and off-chip memory can be managed only by a programmer or compiler. In this paper, we propose a compiler-directed multithreaded SPM data transfer model (MSDTM) to optimize the process of data transfer in a heterogeneous many-core architecture. We use compile-time analysis to classify data accesses, check dependences and determine the allocation of data transfer operations. We further present the data transfer performance model to derive the optimal granularity of data transfer and select the most profitable data transfer strategy. We implement the proposed MSDTM on the GCC complier and evaluate it on Sunway TaihuLight with selected test cases from benchmarks and scientific computing applications. The experimental result shows that the proposed MSDTM improves the application execution time by 5.49$$\times$$ × and achieves an energy saving of 5.16$$\times$$ × on average.

Mobile Networks-on-Chip Mapping Algorithms for Optimization of Latency and Energy Consumption

2021 ◽  
Author(s):  
Arvind Kumar ◽  
Vivek Kumar Sehgal ◽  
Gaurav Dhiman ◽  
S. Vimal ◽  
Ashutosh Sharma ◽  
...  
Keyword(s):  
Energy Consumption ◽  
Mobile Networks ◽  
Mapping Algorithms ◽  
Networks On Chip ◽  
On Chip

The effects of variable mechanical parameters on peak power and energy consumption of ankle-foot prostheses at different speeds

2018 ◽  
Vol 32 (23) ◽  
pp. 1229-1240 ◽  
Author(s):  
Dianbiao Dong ◽  
Bryan Convens ◽  
Yuanxi Sun ◽  
Wenjie Ge ◽  
Pierre Cherelle ◽  
...  
Keyword(s):  
Energy Consumption ◽  
Peak Power ◽  
Mechanical Parameters ◽  
Power And Energy

Characteristics Analyses of Energy Consumption for Boom Closed Circuit of Hydraulic Excavators

2012 ◽  
Vol 170-173 ◽  
pp. 3491-3494
Author(s):  
Ming Dong Chen ◽  
Ding Xuan Zhao
Keyword(s):  
Energy Consumption ◽  
Mathematical Models ◽  
Operating Conditions ◽  
Closed Circuit ◽  
Load Drop ◽  
Hydraulic Pump ◽  
Full Load ◽  
Power Characteristics ◽  
Hydraulic Excavators ◽  
Power And Energy

The boom with closed circuit in Hydraulic Excavators, which is made up of motor, hydraulic pump and accumulator, was put forward based on analysis of the operating condition of ordinary hydraulic excavators and mathematical models of system were built. Power characteristics of main power elements were obtained under typical operating conditions, and then the energy consumption characteristics were analyzed. The results show that the installed power and energy consumption will be reduced using boom with closed circuit, and no-load drop and full load rise of boom are the worst operating conditions.

scholarly journals A New Method for the Calculation of Energy and Power Requirements of Bucket Wheel Excavators

2019 ◽  
Vol 10 (1) ◽  
pp. 15-20
Author(s):  
József András ◽  
József Kovács ◽  
Endre András ◽  
Ildikó Kertész ◽  
Ovidiu Bogdan Tomus
Keyword(s):  
Energy Consumption ◽  
Numerical Method ◽  
Horizontal Plane ◽  
Vertical Plane ◽  
New Method ◽  
Energy Requirements ◽  
Belt Conveyor ◽  
Analytical Formulas ◽  
Power And Energy ◽  
Continuous Working

Abstract The bucket wheel excavator (BWE) is a continuous working rock harvesting device which removes the rock by means of buckets armoured with teeth, mounted on the wheel and which transfers rock on a main hauling system (generally a belt conveyor). The wheel rotates in a vertical plane and swings in the horizontal plane and raised / descended in the vertical plane by a boom. In this paper we propose a graphical-numerical method in order to calculate the power and energy requirements of the main harvesting structure (the bucket wheel) of the BWE. This approach - based on virtual models of the main working units of bucket wheel excavators and their working processes - is more convenient than those based on analytical formulas and simplification hypotheses, and leads to improved operation, reduced energy consumption, increased productivity and optimal use of available actuating power.

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