scholarly journals Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems

2011 ◽  
Vol 2011 ◽  
pp. 1-17 ◽  
Author(s):  
Diana Göhringer ◽  
Jonathan Obie ◽  
André L. S. Braga ◽  
Michael Hübner ◽  
Carlos H. Llanos ◽  
...  
Keyword(s):  
Energy Consumption ◽  
Multiprocessor Systems ◽  
Clock Frequency ◽  
Power Performance ◽  
Frequency Scaling ◽  
Specific System ◽  
Efficient System ◽  
System Solution ◽  
On Chip ◽  
Power And Energy

The design space of FPGA-based processor systems is huge, because many parameters can be modified at design- and runtime to achieve an efficient system solution in terms of performance, power and energy consumption. Such parameters are, for example, the number of processors and their configurations, the clock frequencies at design time, the use of dynamic frequency scaling at runtime, the application task distribution, and the FPGA type and size. The major contribution of this paper is the exploration of all these parameters and their impact on performance, power dissipation, and energy consumption for four different application scenarios. The goal is to introduce a first approach for a developer's guideline, supporting the choice of an optimized and specific system parameterization for a target application on FPGA-based multiprocessor systems-on-chip. The FPGAs used for these explorations were Xilinx Virtex-4 and Xilinx Virtex-5. The performance results were measured on the FPGA while the power consumption was estimated using the Xilinx XPower Analyzer tool. Finally, a novel runtime adaptive multiprocessor architecture for dynamic clock frequency scaling is introduced and used for the performance, power and energy consumption evaluations.

scholarly journals Clock Frequency Impact on the Performance of High-Security Cryptographic Cipher Suites for Energy-Efficient Resource-Constrained IoT Devices

Sensors ◽  
2018 ◽  
Vol 19 (1) ◽  
pp. 15 ◽  
Author(s):  
Manuel Suárez-Albela ◽  
Paula Fraga-Lamas ◽  
Luis Castedo ◽  
Tiago Fernández-Caramés
Keyword(s):  
Energy Consumption ◽  
Transport Layer ◽  
Security Level ◽  
Clock Frequency ◽  
Resource Constrained ◽  
High Security ◽  
Efficient Resource ◽  
Security Levels ◽  
Computationally Intensive ◽  
On Chip

Modern Internet of Things (IoT) systems have to be able to provide high-security levels, but it is difficult to accommodate computationally-intensive cryptographic algorithms on the resource-constrained hardware used to deploy IoT end nodes. Although this scenario brings the opportunity for using advanced security mechanisms such as Transport Layer Security (TLS), several configuration factors impact both the performance and the energy consumption of IoT systems. In this study, two of the most used TLS authentication algorithms (ECDSA and RSA) were compared when executed on a resource-constrained IoT node based on the ESP32 System-on-Chip (SoC), which was tested at different clock frequencies (80, 160 and 240 MHz) when providing different security levels (from 80 to 192 bits). With every tested configuration, energy consumption and average time per transaction were measured. The results show that ECDSA outperforms RSA in all performed tests and that certain software implementations may lead to scenarios where higher security-level alternatives outperform cryptosystems that are theoretically simpler and lighter in terms of energy consumption and data throughput. Moreover, the performed experiments allow for concluding that higher clock frequencies provide better performance in terms of throughput and, in contrast to what may be expected, less energy consumption.

scholarly journals Reducing Power and Energy Consumption of Nonvolatile Microcontrollers with Transparent On-Chip Instruction Cache

2014 ◽  
Vol 05 (11) ◽  
pp. 253-264 ◽  
Author(s):  
Dahoo Kim ◽  
Itaru Hida ◽  
Eric Shun Fukuda ◽  
Tetsuya Asai ◽  
Masato Motomura
Keyword(s):  
Energy Consumption ◽  
Reducing Power ◽  
Instruction Cache ◽  
On Chip ◽  
Power And Energy

Study on the impacts of peaking factors on a water distribution system in Germany

2010 ◽  
Vol 10 (2) ◽  
pp. 165-172 ◽  
Author(s):  
K. Diao ◽  
M. Barjenbruch ◽  
U. Bracklow
Keyword(s):  
Energy Consumption ◽  
Distribution System ◽  
Water Distribution ◽  
Water Distribution System ◽  
Water Distribution Network ◽  
Design Stage ◽  
Water Age ◽  
Specific System ◽  
Average Water

This paper aims to explore the impacts of peaking factors on a water distribution system designed for a small city in Germany through model-based analysis. As a case study, the water distribution network was modelled by EPANET and then two specific studies were carried out. The first study tested corresponding system-wide influences on water age and energy consumption if the peaking factors used at design stage are inconsistent with ones in real situation. The second study inspected the possible relationship between the choice of peaking factors and budgets by comparing several different pipe configurations of the distribution system, obtained according to variety of peaking factors. Given the analysis results, the first study reveals that average water age will increase if peaking factors estimated at design stage are larger than real values in that specific system, and vice versa. In contrast, energy consumption will increase if peaking factors defined for system design are smaller than ones in real case, and vice versa. According to the second study, it might be possible to amplify peaking factors for design dramatically by a slight increase in the investment on this system. However, further study on budget estimation with more factors and detailed information considered should be carried out.

scholarly journals Compiler-directed scratchpad memory data transfer optimization for multithreaded applications on a heterogeneous many-core architecture

2021 ◽  
Author(s):  
Xiaohan Tao ◽  
Jianmin Pang ◽  
Jinlong Xu ◽  
Yu Zhu
Keyword(s):  
Energy Consumption ◽  
High Performance ◽  
Scientific Computing ◽  
Data Transfer ◽  
Performance Model ◽  
Experimental Result ◽  
Transfer Model ◽  
Scratchpad Memory ◽  
On Chip ◽  
Many Core

AbstractThe heterogeneous many-core architecture plays an important role in the fields of high-performance computing and scientific computing. It uses accelerator cores with on-chip memories to improve performance and reduce energy consumption. Scratchpad memory (SPM) is a kind of fast on-chip memory with lower energy consumption compared with a hardware cache. However, data transfer between SPM and off-chip memory can be managed only by a programmer or compiler. In this paper, we propose a compiler-directed multithreaded SPM data transfer model (MSDTM) to optimize the process of data transfer in a heterogeneous many-core architecture. We use compile-time analysis to classify data accesses, check dependences and determine the allocation of data transfer operations. We further present the data transfer performance model to derive the optimal granularity of data transfer and select the most profitable data transfer strategy. We implement the proposed MSDTM on the GCC complier and evaluate it on Sunway TaihuLight with selected test cases from benchmarks and scientific computing applications. The experimental result shows that the proposed MSDTM improves the application execution time by 5.49$$\times$$ × and achieves an energy saving of 5.16$$\times$$ × on average.

Effectiveness of DFS Tuning on Java Server Workload

2015 ◽  
Vol 25 (01) ◽  
pp. 1640005 ◽  
Author(s):  
Hitoshi Oi
Keyword(s):  
Power Consumption ◽  
Sampling Period ◽  
Threshold Level ◽  
Load Level ◽  
Clock Frequency ◽  
Frequency Scaling ◽  
Dynamic Frequency Scaling ◽  
Maximum Reduction ◽  
Dynamic Frequency

Dynamic frequency scaling (DFS) is a feature commonly found in modern processors. It lowers the clock frequency of a core according to the load level and reduces the power consumption. In this paper, we present a case study of tuning DFS parameters on a platform with an AMD Phenom II X6 using the SPECjEnterprise2010 (jEnt10) and SPECjbb2005 (jbb05) as the workload. In jEnt10, a longer sampling period of core utilization (up to 1.5[Formula: see text]s) reduced the power by 6[Formula: see text]Watt at 25% load level. At 50% load level, combining it with an increased threshold level (98%) to switch the clock frequency further reduced the power consumption by up to 10[Formula: see text]Watt. In jbb05, stretching the sampling period was only effective up to 0.5[Formula: see text]s. The maximum reduction was observed at around 60% load level. Raising the threshold level was not effective for jbb05.

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