Three-dimensional integrated circuits (3D-ICs) using through silicon via (TSV) have been developed as an emerging technology that can lead to significant progress (1–4). Among various TSV processes, the via-middle process has potential for wide spread use because formation of small-sized TSVs is relatively easy in the via-middle process. However, TSV reveal process must be performed for electrical contact in the via-middle process. This TSV reveal process is important because it can influence the metal contamination and stacking yield of 3D-ICs. Conventionally, TSV reveal is performed by Si grinding and Si dry etching (5). A disadvantage of that method is the resultant TSV depth deviation, which can cause bonding failure during wafer/chip stacking. In (6), TSV leveling was performed by introducing a chemical mechanical polishing (CMP) step after deposition of the backside insulator. However, the revealed TSVs break during CMP step if they exceed a certain height.
To overcome these problems, we developed a novel TSV reveal process comprising direct Si/Cu grinding and metal contamination removal (7,8). First, simultaneous grinding of Cu and Si was performed using a novel vitrified grinding wheel. In situ cleaning with a high-pressure micro jet and the inelastic porous structure of the grinding wheel suppressed the adhesion of Cu contaminants to the Si, and TSVs were leveled and exposed. Next, an electroless Ni-B film was deposited on the Cu surface of the TSVs. The Si was etched with an alkaline solution, whereas the Cu was protected by the Ni-B film. An insulator was deposited, and then the insulator on the top surface of the TSV was removed. We achieved the backside reveal of TSVs without TSV depth deviation and suppressed Cu contamination to less than 1e11 atoms/cm2. However, after direct Si/Cu grinding with an 8000 grit grinding wheel, the average surface roughness of Si was 5–10 nm, which is larger than that after chemical mechanical polishing (CMP).
In this paper, we developed vitrified grinding wheels with very high grit numbers (#30,000 and #45,000) and present an improved version of our TSV reveal process. The average surface roughness of Si after Si/Cu grinding was approximately 3 nm for the 30,000 grit grinding wheel and 1 nm for the 45,000 grit grinding wheel. This value is equivalent to that after CMP. The improved process produced a uniform reveal of 4-um-diameter TSVs without TSV depth deviation and Cu contamination. The Cu contaminant concentration on Si region between TSVs was small (<3e10 atoms/cm2). This process will reduce the cost of the TSV reveal process and considerably improve the TSV yield.
Realization of high-quality HfO2 on In0.53Ga0.47As by in-situ atomic-layer-deposition