Assessment of XRF Technique as a Method to Measure Percent Ag in SnAg Solders for Flip Chip Applications

2012 ◽  
Vol 2012 (1) ◽  
pp. 000912-000922
Author(s):  
Jennifer D Schuler ◽  
Chia-Hsin Shih ◽  
Charles L Arvin ◽  
KyungMoon Kim ◽  
Eric Perfecto
Keyword(s):  
Cross Sections ◽  
Inductively Coupled Plasma ◽  
Flip Chip ◽  
Spatial Density ◽  
Wafer Level ◽  
Scanning Calorimetry ◽  
Electron Probe Micro Analyzer ◽  
Non Invasive ◽  
Area Of Interest ◽  
Scan Time

Pb-free SnAg solder has become the industry standard for fabricating flip chip interconnects utilizing C4 (controlled collapse chip connection) technology. One area of interest for manufacturability of Pb-free solders is the ability to control and measure the %Ag composition and its variation from wafer to wafer, chip to chip, and C4 to C4. There are various ways to measure solder composition. These are divided into two categories which are invasive and non-invasive referring to whether solder must be removed from the wafer in order to conduct the measurement. There are a variety of invasive methods including Atomic Absorption (AA), Differential Scanning Calorimetry (DSC), Inductively Coupled Plasma (ICP) and Electron Probe Micro-Analyzer (EPMA) used with cross sections. Non-invasive methods are limited, making the development of the non-invasive X-Ray Fluorescence (XRF) method an important technique to determine both the thickness and composition of C4s on wafers without modifying the wafer. There are many factors which can affect the accuracy of the XRF measurements. These include bump geometry, composition, UBM (under bump metallurgy) stack, bump spatial density, underlying chip wiring, tool vibration and tool parameters, such as collimator size, power levels, scan time, etc. This paper will address the implementation issues in utilizing XRF for Pb-free solder SnAg systems. The paper will describe:(1) Experimental bumping variables,(2) XRF configuration, calibration, optimized measuring methodology and the importance of having known standards with the same dimensions of the bumps being measured(3) Measuring accuracy and correlation with ICP and DSC,(4) Ag distribution study in the die and wafer level

A technique for preparing semiconductor cross sections for both TEM and SEM analysis

1989 ◽  
Vol 47 ◽  
pp. 712-713
Author(s):  
Stanley J. Klepeis ◽  
J.P. Benedict ◽  
R.M Anderson
Keyword(s):  
Sample Preparation ◽  
Cross Section ◽  
Cross Sections ◽  
Sem Analysis ◽  
Preparation Technique ◽  
Ion Milling ◽  
Tem Analysis ◽  
Polished Cross Section ◽  
Area Of Interest ◽  
Polished Side

The ability to prepare a cross-section of a specific semiconductor structure for both SEM and TEM analysis is vital in characterizing the smaller, more complex devices that are now being designed and manufactured. In the past, a unique sample was prepared for either SEM or TEM analysis of a structure. In choosing to do SEM, valuable and unique information was lost to TEM analysis. An alternative, the SEM examination of thinned TEM samples, was frequently made difficult by topographical artifacts introduced by mechanical polishing and lengthy ion-milling. Thus, the need to produce a TEM sample from a unique,cross-sectioned SEM sample has produced this sample preparation technique.The technique is divided into an SEM and a TEM sample preparation phase. The first four steps in the SEM phase: bulk reduction, cleaning, gluing and trimming produces a reinforced sample with the area of interest in the center of the sample. This sample is then mounted on a special SEM stud. The stud is inserted into an L-shaped holder and this holder is attached to the Klepeis polisher (see figs. 1 and 2). An SEM cross-section of the sample is then prepared by mechanically polishing the sample to the area of interest using the Klepeis polisher. The polished cross-section is cleaned and the SEM stud with the attached sample, is removed from the L-shaped holder. The stud is then inserted into the ion-miller and the sample is briefly milled (less than 2 minutes) on the polished side. The sample on the stud may then be carbon coated and placed in the SEM for analysis.

scholarly journals Material characterisation of a painted beehive panel by advanced spectroscopic and chromatographic techniques in combination with hyperspectral imaging

2020 ◽  
Vol 8 (1) ◽  
Author(s):  
Klara Retko ◽  
Maša Kavčič ◽  
Lea Legan ◽  
Polonca Ropret ◽  
Bojana Rogelj Škafar ◽  
...  
Keyword(s):  
Raman Spectroscopy ◽  
Hyperspectral Imaging ◽  
Cross Sections ◽  
Extreme Temperature ◽  
Transformation Products ◽  
Paint Layer ◽  
Non Invasive ◽  
Painting Technique ◽  
Invasive Techniques ◽  
Conservation Interventions

AbstractIn this study, a painted beehive panel from the collection of the Slovene Ethnographic Museum was examined with respect to its material composition with the aim to reveal the painting technique. Due to the state of degradation due to outdoor weathering (UV irradiation, rainfall, extreme temperature and humidity fluctuations), as well as past conservation interventions, the object represented a complex analytical challenge. We aimed for non-invasive techniques (FTIR in reflection mode, Raman spectroscopy and hyperspectral imaging in the range of 400–2500 nm); however, in order to explore paint layers, cross-sections were also analysed using Raman spectroscopy. FTIR spectroscopy in transmission mode and gas chromatography coupled to mass spectrometry were also used on sample fragments. Various original materials were identified such as pigments and binders. The surface coating applied during conservation interventions was also characterised. Additionally, organic compounds were found (oxalate, carboxylate), representing transformation products. The potential use of Prussian blue as a background paint layer is discussed.

Wafer-Scale, Highly-Ordered Silicon Nanowires Produced by Step-and-Flash Imprint Lithography and Metal-Assisted Chemical Etching

2012 ◽  
Vol 1512 ◽  
Author(s):  
Jian-Wei Ho ◽  
Qixun Wee ◽  
Jarrett Dumond ◽  
Li Zhang ◽  
Keyan Zang ◽  
...  
Keyword(s):  
Aspect Ratio ◽  
Cross Sections ◽  
Silicon Nanowires ◽  
High Aspect Ratio ◽  
Chemical Etching ◽  
Semiconductor Device ◽  
Imprint Lithography ◽  
Wafer Level ◽  
Conventional Photolithography ◽  
Metal Assisted Chemical Etching

ABSTRACTA combinatory approach of Step-and-Flash Imprint Lithography (SFIL) and Metal-Assisted Chemical Etching (MacEtch) was used to generate near perfectly-ordered, high aspect ratio silicon nanowires (SiNWs) on 4" silicon wafers. The ordering and shapes of SiNWs depends only on the SFIL nanoimprinting mould used, thereby enabling arbitary SiNW patterns not possible with nanosphere and interference lithography (IL) to be generated. Very densely packed SiNWs with periodicity finer than that permitted by conventional photolithography can be produced. The height of SiNWs is, in turn, controlled by the etching duration. However, it was found that very high aspect ratio SiNWs tend to be bent during processing. Hexagonal arrays of SiNW with circular and hexagonal cross-sections of dimensions 200nm and less were produced using pillar and pore patterned SFIL moulds. In summary, this approach allows highlyordered SiNWs to be fabricated on a wafer-level basis suitable for semiconductor device manufacturing.

Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages (WLCSP)

2011 ◽  
Author(s):  
Pushkraj Tumne ◽  
Vikram Venkatadri ◽  
Santosh Kudtarkar ◽  
Michael Delaus ◽  
Daryl Santos ◽  
...  
Keyword(s):  
Flip Chip ◽  
Bulk Solder ◽  
Consumer Electronics ◽  
Drop Test ◽  
Design Parameters ◽  
Mechanical Shock ◽  
Wafer Level ◽  
Cross Sectional ◽  
Right Censored Data ◽  
Solder Balls

Today’s consumer market demands electronics that are smaller, faster and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer Level Chip Scale Package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence the emphasis of reliability is shifting towards study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the PCB by solder balls. The size of these solder balls is typically large enough (300μm pre-reflow for 0.5mm pitch and 250μm pre-reflow for 0.4mm pitch) to avoid use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different Silver (Ag) content, backside lamination with different thickness, WLCSP type –Direct and Re-Distribution Layer (RDL), bond pad thickness, and sputtered versus electroplated Under Bump Metallurgy (UBM) deposition methods for 8×8, 9×9, and 10×10 array sizes. The test vehicles built using these design parameters were drop tested using JEDEC recommended test boards and conditions as per JESD22-B11. Cross sectional analysis was used to identify, confirm, and classify the intermetallic, and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data was collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and un-grouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

Microstructural Features and Properties of Al-Cu-Mg Alloy Containing Silver and Cerium

2021 ◽  
Vol 316 ◽  
pp. 533-537
Author(s):  
Pavel L. Reznik ◽  
Boris V. Ovsyannikov
Keyword(s):  
Heat Treatment ◽  
Mechanical Characteristics ◽  
Dendritic Segregation ◽  
Scanning Calorimetry ◽  
Electron Probe Micro Analyzer ◽  
Melting Temperatures ◽  
Heat Treatment Mode ◽  
Cast Condition ◽  
Component Phase ◽  
Non Equilibrium

The article presents the results of an investigation of microstructural features and mechanical characteristics of Al-5.0Cu-0.5Mg alloy containing up to 0.4 wt. % Ag and up to 0.1 wt. % Ce. The experiment was conducted using optical microscopy, Scanning Electron Microscopy as well as an electron probe micro-analyzer and Differential Scanning Calorimetry. Samples in cast condition and after heat treatment were examined. The melting temperatures of non-equilibrium eutectics (non-equilibrium solidus), equilibrium solidus and liquidus were determined. The optimal temperature of the homogenizing heat treatment was determined, which was 500°C. Using this heat treatment mode resulted in the elimination of dendritic segregation and complete dissolution of silver in aluminum. Injection of cerium into the Al-Cu-Mg-Ag system during crystallization of the melt is accompanied by the formation of a coarse four-component phase, which has the morphology of polyhedrons, is on the grain boundaries. The estimation of the relation between microstructure characteristics and mechanical properties of the alloy has been made.

Parametric Design and Reliability Analysis of WIT Wafer Level Packaging

2000 ◽  
Author(s):  
Y. T. Lin ◽  
P. J. Tang ◽  
K. N. Chiang
Keyword(s):  
Reliability Analysis ◽  
Flip Chip ◽  
Parametric Design ◽  
Material Selection ◽  
New Technology ◽  
Rapid Expansion ◽  
Wafer Level ◽  
Good Reliability ◽  
Wafer Level Packaging ◽  
Wafer Level Package

Abstract The demands of electronic packages toward lower profile, lighter weight, and higher density of I/O lead to rapid expansion in the field of flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent needs of high I/O density and good reliability characteristic lead to the evolution of the ultra high-density type of non-solder interconnection such as the wire interconnect technology (WIT). The new technology using copper posts to replace the solder bumps as interconnections shown a great improvement in the reliability life. Moreover, this type of wafer level package could achieve higher I/O density, as well as ultra fine pitch. This research will focus on the reliability analysis of the WIT package structures in material selection and structural design, etc. This research will use finite element method to analyze the physical behavior of packaging structures under thermal cycling condition to compare the reliability characteristics of conventional wafer level package and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature dependent material properties will be applied to all of the models.

Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications

2002 ◽  
Vol 124 (3) ◽  
pp. 205-211 ◽  
Author(s):  
John H. Lau ◽  
S. W. Ricky Lee ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Cross Sections ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Circuit Board ◽  
Test Results ◽  
Pcb Assembly ◽  
Creep Analysis ◽  
Chip Scale Package ◽  
Time Dependent Analysis

An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton’s creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the thermal cycling test results of the micro VIP CSP PCB assembly is presented.

scholarly journals Czochralski growth and spectroscopic investigations of Yb3+, La3+:Na2SO4(I) and Nd3+:Na2SO4(I)

1999 ◽  
Vol 14 (10) ◽  
pp. 4093-4097 ◽  
Author(s):  
Patric Mikhail ◽  
Reto Basler ◽  
Jürg Hulliger
Keyword(s):  
Cross Sections ◽  
Inductively Coupled Plasma ◽  
Stimulated Raman Scattering ◽  
Optical Emission ◽  
Czochralski Method ◽  
Distribution Coefficients ◽  
Czochralski Growth ◽  
Inductively Coupled ◽  
Spectroscopic Investigations ◽  
New Material

Ln3+-stabilized Na2SO4 (phase I) single crystals were grown by the Czochralski method. Differential thermal analysis revealed the influence of the ionic radius of Ln3+ on the stabilization of Na2SO4(I). Distribution coefficients (∼0.8–1.1) were measured by the inductively coupled plasma optical emission spectroscopy method and x-ray fluorescence spectroscopy. Spectroscopic investigations yielded absorption cross sections of 0.6 × 10−20 cm2 (π-polarized, 928.5 nm) and 1.5 × 10−20 cm2 (π-polarized, 797.3 nm) for Yb3+, La3+:Na2SO4 and Nd3+:Na2SO4, respectively. Crystal growth of Gd3+-stabilized Na2SO4(I) provides an interesting new material for stimulated Raman scattering experiments.

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