Thin-Film Signal and Power Redistribution Layers Based on AL-X and Cu

2012 ◽  
Vol 2012 (1) ◽  
pp. 000326-000333
Author(s):  
John Bailey ◽  
Alexander Pfeiffenberger ◽  
Charles Ellis ◽  
Mike Palmer ◽  
Tamara Issac-Smith ◽  
...  
Keyword(s):  
Thin Film ◽  
Transmission Line ◽  
Power Distribution ◽  
High Speed ◽  
Signal Transmission ◽  
Integrated Systems ◽  
Copper Metallization ◽  
Strip Line ◽  
Signal Loss ◽  
Wafer Level

Use of unpackaged die in advanced integrated systems (i.e., 3-D integrated systems) calls for dense interconnection schemes with controlled impedance for high-speed signal routing and minimal impedance for efficient power distribution. We have evaluated a new material set for use in a thin-film-based redistribution layer (RDL) that consists of Asahi Glass AL-X spin-on low-k dielectric polymer and electroplated copper metallization. This technology allows fan-out and interconnection of high-speed signals and power to/from die pads on pitches sufficiently less than 100 μm directly to companion die over short distances or for transition to underlying board metallization for longer transmission distances that may require lower signal loss. This technology is demonstrated using Si wafers onto which the thin-film RDL is fabricated. We have developed and described the fabrication procedures used to construct multiple interconnected layers of AL-X / Cu, which are compatible with standard wafer level packaging (WLP) processes. We have also evaluated the performance of this technology for high-speed digital signal transmission by characterizing frequency parameters (i.e., S parameters) of single-ended and differential strip-line transmission line structures. We have optimized transmission line geometries for transmission of signals at rates greater than 25 Gbps. In addition to high-speed signal redistribution capabilities, we have characterized power redistribution capabilities of this technology. Results of the signal and power integrity measurements and simulations performed in this work are presented.

Electrical Characterization on a High-Speed Wafer-Level Package

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001937-001962
Author(s):  
Kai Liu ◽  
YongTaek Lee ◽  
HyunTai Kim ◽  
MaPhooPwint Hlaing ◽  
Susan Park ◽  
...  
Keyword(s):  
High Speed ◽  
Unit Length ◽  
Ground Plane ◽  
Measurement Data ◽  
Electrical Characterization ◽  
Electrical Performance ◽  
Metal Loss ◽  
Signal Loss ◽  
Wafer Level ◽  
Wafer Level Package

In this paper, a 2-layer eWLB (embedded Wafer-Level BGA) is studied and its performance is compared with an equivalent 4-layer laminate package. Since eWLB package is processed by using lithographical method, design rules on width (W) and spacing (S) are much finer (usually 2–3 times finer) than those for laminate package. In other words, signal traces can be implemented in smaller fan-out regions. The smaller feature sizes for signal traces would end up with more metal loss per unit length. But as the signal traces can be implemented in smaller fan-out regions, overall trace-routing may be shorter, and equivalent insertion-loss may be achieved. In eWLB, the ground plane is closer to the signal traces. This actually helps to reduce cross-talk between wide I/O buses, as the electrical field is contained in a smaller region by the closer ground plane. Another key advantage from wafer-level package is a smoother metal surface, which greatly reduces the extra signal loss, due to surface-roughness effect, especially for higher-frequency and higher-speed applications. In addition, through-via structures for wafer-level package are typically 2–3 times smaller. This allows to implement power/ground planes in a more continuous way, achieving better resistance and inductance for power/ground nets. Overall electrical performance, which takes into account of all the impacts above, can be evaluated by signal-integrity analysis (E-diagram). Measurement data of a 2-layer eWLB package for a LPDDR application will be presented, which shows the comparable performance typically obtained from a 4-layer laminate package

Low Permittivity SiO2/Void Nanocomposite Films

1986 ◽  
Vol 72 ◽  
Author(s):  
Amitabh Das ◽  
R. Messier ◽  
T. R. Gururaja ◽  
L. E. Cross
Keyword(s):  
Thin Film ◽  
High Speed ◽  
Columnar Structure ◽  
Nanocomposite Films ◽  
Strip Line ◽  
Gel Layer ◽  
Novel Approach ◽  
Sputter Deposited ◽  
Low Permittivity ◽  
Potential Use

AbstractA novel approach for preparing porous SiO2 thin films by sputter deposi-tion is being developed. The porosity is introduced to reduce the dielectric permittivity of the film to less than 3 for potential use in packaging high speed VLSIs. In the first approach, amorphous silicon is initially deposited to produce a columnar structure with a thickness of 25μm, followed by etching and thermal oxidation to result in closely spaced SiO2 pillars. Capping the structure by a thin film (0.1μm), silica gel layer provides the support for strip line traces. In the second approach, porous SiO2 films are prepared by reactive sputtering. The dielectric properties of the sputter deposited SiO2 films are presented.

Analysis of Thin Film Optical Filters Using Transmission Line Models

1994 ◽  
Vol 23 (1) ◽  
pp. 39-43
Author(s):  
B. Lakshmi ◽  
K. R. Suresh Nair ◽  
Y. G. K. Patro ◽  
B. M. Arora
Keyword(s):  
Thin Film ◽  
Transmission Line ◽  
Optical Filters ◽  
Transmission Line Models
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