High Temperature Packaging for SiC Power Transistors

2012 ◽  
Vol 2012 (1) ◽  
pp. 001124-001130
Author(s):  
K. Brinkfeldt ◽  
T. Åklint ◽  
C. Sandberg ◽  
P. Johander ◽  
D. Andersson
Keyword(s):  
High Temperature ◽  
Room Temperature ◽  
Wide Band ◽  
Stress Concentrations ◽  
Wide Band Gap ◽  
Packaging Process ◽  
Power Transistors ◽  
Silicon Devices ◽  
Chemical Inertness ◽  
High Temperature Operation

Power transistors based on silicon carbide (SiC) are now commercially available. They have a higher efficiency and higher voltage blocking capabilities than conventional silicon devices. The wide-band gap and chemical inertness of SiC makes it suitable to high temperature operation. However, there is a need for new packaging for power transistors that can operate in higher temperatures. We have developed a package based on ceramics and silver for high temperature operation of SiC power transistors. Three types of SiC devices from different manufacturers are packaged and tested in room temperature. Though the devices were still functional after the packaging process, their performance seem to have degraded. This could be a result of the high temperature packaging process and the measurement setup. FEM simulations are also performed to investigate the thermo-mechanical behavior of the package. The target operating temperature of the package is 400 °C. Modeling show stress concentrations at the corners of the device chip and suggests that this stress is decreased if the substrate metallization is changed from copper to silver.

High Temperature Silicon Carbide CMOS Integrated Circuits

2011 ◽  
Vol 679-680 ◽  
pp. 726-729 ◽  
Author(s):  
David T. Clark ◽  
Ewan P. Ramsay ◽  
A.E. Murphy ◽  
Dave A. Smith ◽  
Robin. F. Thompson ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
High Temperature ◽  
Integrated Circuits ◽  
Band Gap ◽  
High Temperatures ◽  
Wide Band ◽  
Cmos Technology ◽  
Cmos Integrated Circuits ◽  
Wide Band Gap ◽  
Circuit Performance

The wide band-gap of Silicon Carbide (SiC) makes it a material suitable for high temperature integrated circuits [1], potentially operating up to and beyond 450°C. This paper describes the development of a 15V SiC CMOS technology developed to operate at high temperatures, n and p-channel transistor and preliminary circuit performance over temperature achieved in this technology.

1700V, 5.5mOhm-cm2 4H-SiC DMOSFET with Stable 225°C Operation

2014 ◽  
Vol 778-780 ◽  
pp. 903-906 ◽  
Author(s):  
Kevin Matocha ◽  
Kiran Chatty ◽  
Sujit Banerjee ◽  
Larry B. Rowland
Keyword(s):  
High Temperature ◽  
Temperature Stress ◽  
High Temperatures ◽  
Threshold Voltage ◽  
Room Temperature ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Device Reliability ◽  
Bias Temperature Stress ◽  
High Temperature Operation

We report a 1700V, 5.5mΩ-cm24H-SiC DMOSFET capable of 225°C operation. The specific on-resistance of the DMOSFET designed for 1200V applications is 8.8mΩ-cm2at 225°C, an increase of only 60% compared to the room temperature value. The low specific on-resistance at high temperatures enables a smaller die size for high temperature operation. Under a negative gate bias temperature stress (BTS) at VGS=-15 V at 225°C for 20 minutes, the devices show a threshold voltage shift of ΔVTH=-0.25 V demonstrating one of the key device reliability requirements for high temperature operation.

Test Results of Sintered Nanosilver Paste Die Attach for High-Temperature Applications

2016 ◽  
Vol 13 (1) ◽  
pp. 6-16 ◽  
Author(s):  
Paul Croteau ◽  
Sayan Seal ◽  
Ryan Witherell ◽  
Michael Glover ◽  
Shashank Krishnamurthy ◽  
...  
Keyword(s):  
High Temperature ◽  
Cooling System ◽  
Wide Band ◽  
Power Converter ◽  
Test Results ◽  
Wide Band Gap ◽  
Strain Behavior ◽  
Die Attach ◽  
Nanosilver Paste ◽  
Sintered Silver

The emergence of wide band gap devices has pushed the boundaries of power converter operations and high power density applications. It is desirable to operate a power inverter at high switching frequencies to reduce passive filter weight and at high temperature to reduce the cooling system requirement. Therefore, materials and components that are reliable at temperatures ranging from −55°C to 200°C, or higher, are needed. Sintered silver is receiving significant attention in the power electronic industry. The porous nature of sintered nanosilver paste with a reduced elastic modulus has the potential to provide strain relief between the die component and substrate while maintaining its relatively high melting point after sintering. The test results presented herein include tensile testing to rupture of sintered silver film to characterize stress-strain behavior, as well as die shear and thermal cyclic tests of sintered silver-bonded silicon die specimens to copper substrates to determine shear strength and reliability.

scholarly journals Semiconducting polymer blends that exhibit stable charge transport at high temperatures

Science ◽  
2018 ◽  
Vol 362 (6419) ◽  
pp. 1131-1134 ◽  
Author(s):  
Aristide Gumyusenge ◽  
Dung T. Tran ◽  
Xuyi Luo ◽  
Gregory M. Pitch ◽  
Yan Zhao ◽  
...  
Keyword(s):  
High Temperature ◽  
Polymer Blends ◽  
Charge Transport ◽  
Organic Semiconductors ◽  
Room Temperature ◽  
Elevated Temperatures ◽  
Hole Mobility ◽  
General Strategy ◽  
Semiconducting Polymer ◽  
High Temperature Operation

Although high-temperature operation (i.e., beyond 150°C) is of great interest for many electronics applications, achieving stable carrier mobilities for organic semiconductors at elevated temperatures is fundamentally challenging. We report a general strategy to make thermally stable high-temperature semiconducting polymer blends, composed of interpenetrating semicrystalline conjugated polymers and high glass-transition temperature insulating matrices. When properly engineered, such polymer blends display a temperature-insensitive charge transport behavior with hole mobility exceeding 2.0 cm2/V·s across a wide temperature range from room temperature up to 220°C in thin-film transistors.

Some studies on highly transparent wide band gap indium molybdenum oxide thin films rf sputtered at room temperature

2008 ◽  
Vol 516 (7) ◽  
pp. 1359-1364 ◽  
Author(s):  
E. Elangovan ◽  
A. Marques ◽  
A.S. Viana ◽  
R. Martins ◽  
E. Fortunato
Keyword(s):  
Thin Films ◽  
Band Gap ◽  
Molybdenum Oxide ◽  
Room Temperature ◽  
Wide Band ◽  
Oxide Thin Films ◽  
Wide Band Gap

OPTICAL ABSORPTION BEHAVIOR OF Co (II) ION DOPED PVA ASSISTED CdSe NANOPARTICLES

2013 ◽  
Vol 22 ◽  
pp. 346-350
Author(s):  
K. RAVINDRANADH ◽  
R. V. S. S. N. RAVIKUMAR ◽  
M. C. RAO
Keyword(s):  
Band Gap ◽  
Room Temperature ◽  
Urbach Energy ◽  
Wavelength Region ◽  
Wide Band ◽  
Cdse Nanoparticles ◽  
Poly Vinyl Alcohol ◽  
Wide Band Gap ◽  
Direct Band ◽  
Bulk Band

CdSe is an important II-VI, n-type direct band gap semiconductor with wide band gap (bulk band gap of 2.6 eV) and an attractive host for the development of doped nanoparticles. Poly vinyl alcohol (PVA) is used as a capping agent to stabilize the CdSe nanoparticles. The optical properties of Co (II) ion doped PVA capped CdSe nanoparticles grown at room temperature are studied in the wavelength region of 200-1400 nm. The spectrum of Co (II) ion doped PVA capped CdSe nanoparticles exhibit five bands at 1185, 620, 602, 548 and 465 nm (8437, 16125, 16607, 18243 and 21499 cm-1). The bands observed at 1185, 548 and 465 nm are correspond to the three spin allowed transitions 4T1g (F) → 4T2g (F), 4T1g (F) → 4A2g (F) and 4T1g (F) → 4T1g (P) respectively. The other bands observed at 602 nm and 620 nm are assigned to spin forbidden transitions 4T1g (F) → 2T2g (G), 4T1g (F) → 2T1g (G) . The small value of the Urbach energy indicates greater stability of the prepared sample.

Normally-off GaN MOSFETs on Silicon Substrates with High-temperature Operation

2009 ◽  
Vol 1202 ◽  
Author(s):  
Hiroshi Kambayashi ◽  
Yuki Niiyama ◽  
Takehiko Nomura ◽  
Masayuki Iwami ◽  
yoshihiro Satoh ◽  
...  
Keyword(s):  
High Temperature ◽  
Room Temperature ◽  
Silicon Substrates ◽  
Enhancement Mode ◽  
Threshold Voltages ◽  
Source Voltage ◽  
Gan Hfet ◽  
Output Characteristics ◽  
High Temperature Operation ◽  
State Resistance

AbstractWe have demonstrated enhancement-mode n-channel gallium nitride (GaN) MOSFETs on Si (111) substrates with high-temperature operation up to 300 °C. The GaN MOSFETs have good normally-off operation with the threshold voltages of +2.7 V. The MOSFET exhibits good output characteristics from room temperature to 300 °C. The leakage current at 300°C is less than 100 pA/mm at the drain-to-source voltage of 0.1 V. The on-state resistance of MOSFET at 300°C is about 1.5 times as high as that at room temperature. These results indicate that GaN MOSFET is suitable for high-temperature operation compared with AlGaN/GaN HFET.

Package Design and Analysis for Vertical Gallium Nitride Field Effect Transistors

2021 ◽  
Vol 2021 (HiTEC) ◽  
pp. 000058-000063
Author(s):  
John Harris ◽  
David Huitink ◽  
Dan Ewing
Keyword(s):  
Gallium Nitride ◽  
High Temperature ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Wide Band ◽  
Development Stage ◽  
Wide Band Gap ◽  
Package Design ◽  
Bulk Gan ◽  
Effect Transistor

Abstract Gallium nitride (GaN) is a wide band gap semi-conductor with superior electron mobility to silicon carbide. These properties allow for the design of high temperature capable devices with excellent on resistance and breakdown voltage for their size. However, bulk GaN is difficult to fabricate and doping for field effect transistor (FET) control has been elusive, so vertical GaN devices are not commonplace. This paper measures the characteristics of vertical GaN FETs in the development stage and discusses packaging them for fabrication feedback and for future high temperature aplications.

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