scholarly journals Head-on-Pillow Defect Detection: X-Ray Inspection Limitations

2019 ◽  
Vol 16 (2) ◽  
pp. 91-102
Author(s):  
Lars Bruno ◽  
Benny Gustafson
Keyword(s):  
Solder Joints ◽  
Solder Paste ◽  
Wafer Level ◽  
Reflow Soldering ◽  
X Ray ◽  
Soldering Process ◽  
Irregular Shapes ◽  
Fine Pitch ◽  
Solder Balls ◽  
Ball Grid Array Packages

Abstract Both the number and the variants of ball grid array packages (BGAs) are tending to increase on network printed board assemblies with sizes ranging from a few millimeter die size wafer level packages with low ball count to large multidie system-in-package (SiP) BGAs with 60–70 mm side lengths and thousands of I/Os. One big challenge, especially for large BGAs, SiPs, and for thin fine-pitch BGA assemblies, is the dynamic warpage during the reflow soldering process. This warpage could lead to solder balls losing contact with the solder paste and its flux during parts of the soldering process, and this may result in solder joints with irregular shapes, indicating poor or no coalescence between the added solder and the BGA balls. This defect is called head-on-pillow (HoP) and is a failure type that is difficult to determine. In this study, x-ray inspection was used as a first step to find deliberately induced HoP defects, followed by prying off of the BGAs to verify real HoP defects and the fault detection correlation between the two methods. The result clearly shows that many of the solder joints classified as potential HoP defects in the x-ray analysis have no evidence at all of HoP after pry-off. This illustrates the difficulty of determining where to draw the line between pass and fail for HoP defects when using x-ray inspection.

Convection vs vapour phase reflow in LED and BGA assembly

2018 ◽  
Vol 30 (2) ◽  
pp. 87-99 ◽  
Author(s):  
Barbara Dziurdzia ◽  
Maciej Sobolewski ◽  
Janusz Mikolajek
Keyword(s):  
Statistical Analysis ◽  
Solder Joints ◽  
Void Formation ◽  
Vapour Phase ◽  
Distribution Data ◽  
Solder Paste ◽  
Content Type ◽  
X Ray ◽  
Bga Packages ◽  
Solder Balls

Purpose The aim of this paper is to evaluate using statistical methods how two soldering techniques – the convection reflow and vapour phase reflow with vacuum – influence reduction of voids in lead-free solder joints under Light Emitted Diodes (LEDs) and Ball Grid Arrays (BGAs). Design/methodology/approach Distribution of voids in solder joints under thermal and electrical pads of LEDs and in solder balls of BGAs assembled with convection reflow and vapour phase reflow with vacuum has been investigated in terms of coverage or void contents, void diameters and number of voids. For each soldering technology, 80 LEDs and 32 solder balls in BGAs were examined. Soldering processes were carried out in the industrial or semi-industrial environment. The OM340 solder paste of Innolot type was used for LED soldering. Voidings in solder joints were inspected with a 2D X-ray transmission system. OriginLab was used for statistical analysis. Findings Investigations supported by statistical analysis showed that the vapour phase reflow with vacuum decreases significantly void contents and number and diameters of voids in solder joints under LED and BGA packages when compared to convection reflow. Originality/value Voiding distribution data were collected on the basis of 2D X-ray images for test samples manufactured during the mass production processes. Statistical analysis enabled to appraise soldering technologies used in these processes in respect of void formation.

Quantitative Evaluation of Voids in Lead Free Solder Joints

2015 ◽  
Vol 772 ◽  
pp. 284-289 ◽  
Author(s):  
Sabuj Mallik ◽  
Jude Njoku ◽  
Gabriel Takyi
Keyword(s):  
Solder Bump ◽  
Solder Joints ◽  
Void Formation ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
X Ray ◽  
Size And Shape ◽  
Solder Bumps ◽  
Free Solder

Voiding in solder joints poses a serious reliability concern for electronic products. The aim of this research was to quantify the void formation in lead-free solder joints through X-ray inspections. Experiments were designed to investigate how void formation is affected by solder bump size and shape, differences in reflow time and temperature, and differences in solder paste formulation. Four different lead-free solder paste samples were used to produce solder bumps on a number of test boards, using surface mount reflow soldering process. Using an advanced X-ray inspection system void percentages were measured for three different size and shape solder bumps. Results indicate that the voiding in solder joint is strongly influenced by solder bump size and shape, with voids found to have increased when bump size decreased. A longer soaking period during reflow stage has negatively affectedsolder voids. Voiding was also accelerated with smaller solder particles in solder paste.

X-ray inspection and Six-Sigma in analysis of LED thermal pad coverage

2017 ◽  
Vol 29 (1) ◽  
pp. 28-33 ◽  
Author(s):  
Barbara Dziurdzia ◽  
Janusz Mikolajek
Keyword(s):  
Six Sigma ◽  
Vapour Phase ◽  
Inspection System ◽  
Solder Paste ◽  
Process Variables ◽  
Reflow Soldering ◽  
Content Type ◽  
X Ray ◽  
Solder Pastes ◽  
Free Solder

Purpose The purpose of this paper is to evaluate selected methods of reduction voidings in lead-free solder joints underneath thermal pads of light-emitting diodes (LEDs), using X-ray inspection and Six Sigma methodology. Design/methodology/approach On the basis of cause and effect diagram for solder voiding, the potential causes of voids and influence of process variables on void formation were found. Three process variables were chosen: the type of reflow soldering, vacuum incorporation and the type of solder paste. Samples of LEDs were mounted with convection and vapour phase reflow soldering. Vacuum was incorporated into vapour phase soldering. Two types of solder pastes OM338PT and LFS-216LT were used. Algorithm incorporated into X-ray inspection system enabled to calculate the statistical distribution of LED thermal pad coverage and to find the process capability index (Cpk) of applied soldering techniques. Findings The evaluation of selected soldering processes of LEDs in respect of their thermal pad coverage and statistical Cpk indices is presented. Vapour-phase soldering with vacuum is capable (Cpk > 1) for OM338PT and LFS-216LT paste. Convection reflow without vacuum with LFS-216LT paste is also capable (Cpk = 1.1). Other technological soldering processes require improvements. Vacuum improves radically the capability of a reflow soldering for an LED assembly. When vacuum is not accessible, some improvement of capability to a lower extent is possible by an application of void-free solder pastes. Originality/value Six Sigma statistical methodology combined with X-ray diagnosis was used to check whether applied methods of void reduction underneath LED thermal pads are capable processes.

SAC–xTiO2 nano-reinforced lead-free solder joint characterizations in ultra-fine package assembly

2018 ◽  
Vol 30 (1) ◽  
pp. 1-13 ◽  
Author(s):  
Fakhrozi Che Ani ◽  
Azman Jalar ◽  
Abdullah Aziz Saad ◽  
Chu Yee Khor ◽  
Roslina Ismail ◽  
...  
Keyword(s):  
Electron Microscope ◽  
Solder Joint ◽  
Solder Joints ◽  
Ion Beam ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Content Type ◽  
X Ray ◽  
Free Solder

Purpose This paper aims to investigate the characteristics of ultra-fine lead-free solder joints reinforced with TiO2 nanoparticles in an electronic assembly. Design/methodology/approach This study focused on the microstructure and quality of solder joints. Various percentages of TiO2 nanoparticles were mixed with a lead-free Sn-3.5Ag-0.7Cu solder paste. This new form of nano-reinforced lead-free solder paste was used to assemble a miniature package consisting of an ultra-fine capacitor on a printed circuit board by means of a reflow soldering process. The microstructure and the fillet height were investigated using a focused ion beam, a high-resolution transmission electron microscope system equipped with an energy dispersive X-ray spectrometer (EDS), and a field emission scanning electron microscope coupled with an EDS and X-ray diffraction machine. Findings The experimental results revealed that the intermetallic compound with the lowest thickness was produced by the nano-reinforced solder with a TiO2 content of 0.05 Wt.%. Increasing the TiO2 content to 0.15 Wt.% led to an improvement in the fillet height. The characteristics of the solder joint fulfilled the reliability requirements of the IPC standards. Practical implications This study provides engineers with a profound understanding of the characteristics of ultra-fine nano-reinforced solder joint packages in the microelectronics industry. Originality/value The findings are expected to provide proper guidelines and references with regard to the manufacture of miniaturized electronic packages. This study also explored the effects of TiO2 on the microstructure and the fillet height of ultra-fine capacitors.

Electrical resistance of Sn–Ag–Cu ball grid array packages with Sn–Zn–Bi addition jointed at 240 °C

2007 ◽  
Vol 22 (1) ◽  
pp. 113-123
Author(s):  
Po-Cheng Shih ◽  
Kwang-Lung Lin
Keyword(s):  
Control System ◽  
Intermetallic Compound ◽  
Aging Time ◽  
Electrical Resistance ◽  
Ball Grid Array ◽  
Solder Paste ◽  
Solder Balls ◽  
Solder Bulk ◽  
Ball Grid Array Packages

Sn–8Zn–3Bi solder paste and Sn–3.2Ag–0.5Cu solder balls were reflowed simultaneously at 240 °C on Cu/Ni/Au metallized ball grid array substrates. The joints without Sn–Zn–Bi addition (only Sn–Ag–Cu) were studied as a control system. Electrical resistance was measured after multiple reflows and aging. The electrical resistance of the joint (R1) consisted of three parts: the solder bulk (Rsolder bulk, upper solder highly beyond the mask), interfacial solder/intermetallic compound (Rsolder/IMC), and the substrate (Rsubstrate). R1 increased with reflows and aging time. Rsolder/IMC, rather than Rsolder bulk and Rsubstrate, seemed to increase with reflows and aging time. The increase of R1 was ascribed to the Rsolder/IMC rises. Rsubstrate was the major contribution to R1. However Rsolder/IMC dominated the increase of R1 with reflows and aging. R1 of Sn–Zn–Bi/Sn–Ag–Cu samples were higher than that of Sn–Ag–Cu samples in various tests.

Thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components: a review

2016 ◽  
Vol 28 (2) ◽  
pp. 41-62 ◽  
Author(s):  
Chun Sean Lau ◽  
C.Y. Khor ◽  
D. Soares ◽  
J.C. Teixeira ◽  
M.Z. Abdullah
Keyword(s):  
Solder Joints ◽  
Simulation Modelling ◽  
Lead Free ◽  
Lead Free Solder ◽  
Reflow Process ◽  
Reflow Soldering ◽  
Content Type ◽  
Surface Mount ◽  
Soldering Process ◽  
Free Solder

Purpose The purpose of the present study was to review the thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components (SMCs). The topics of the review include challenges in modelling of the reflow soldering process, optimization and the future challenges in the reflow soldering process. Besides, the numerical approach of lead-free solder reliability is also discussed. Design/methodology/approach Lead-free reflow soldering is one of the most significant processes in the development of surface mount technology, especially toward the miniaturization of the advanced SMCs package. The challenges lead to more complex thermal responses when the PCB assembly passes through the reflow oven. The virtual modelling tools facilitate the modelling and simulation of the lead-free reflow process, which provide more data and clear visualization on the particular process. Findings With the growing trend of computer power and software capability, the multidisciplinary simulation, such as the temperature and thermal stress of lead-free SMCs, under the influenced of a specific process atmosphere can be provided. A simulation modelling technique for the thermal response and flow field prediction of a reflow process is cost-effective and has greatly helped the engineer to eliminate guesswork. Besides, simulated-based optimization methods of the reflow process have gained popularity because of them being economical and have reduced time-consumption, and these provide more information compared to the experimental hardware. The advantages and disadvantages of the simulation modelling in the reflow soldering process are also briefly discussed. Practical implications This literature review provides the engineers and researchers with a profound understanding of the thermo-mechanical challenges of reflowed lead-free solder joints in SMCs and the challenges of simulation modelling in the reflow process. Originality/value The unique challenges in solder joint reliability, and direction of future research in reflow process were identified to clarify the solutions to solve lead-free reliability issues in the electronics manufacturing industry.

An Investigation of the Lead-Free Surface Mount Soldering Process: Solder Joint Evaluation and Process Optimisation

2004 ◽  
Author(s):  
Claire Ryan ◽  
Jeff M. Punch ◽  
Bryan Rodgers ◽  
Greg Heaslip ◽  
Shane O’Neill ◽  
...  
Keyword(s):  
Screen Printing ◽  
Solder Joints ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Surface Mount ◽  
Snagcu Solder ◽  
Soldering Process ◽  
Free Process ◽  
Free Solder

A European Union ban on lead in most electrical and electronic equipment will be imposed as of July 1st 2006. The ban, along with market pressures, means that manufacturers must transfer from a tin-lead soldering process to a lead-free process. In this paper the implications on the surface mount (SMT) soldering process are presented. A set of experiments was conducted to investigate the screen-printing and reflow steps of the SMT process using a tin-silver-copper (95.5Sn3.8Ag0.7Cu) solder and a baseline of standard tin-lead (63Sn37Pb). 10×10 arrays of micro Ball Grid Array (micro-BGA) components mounted on 8-layer FR4 printed wiring boards (PWBs) were used. The screen-printing experiment addressed the deposition of the solder paste on the board. The parameters used in the investigation were print speed, squeegee pressure, snap-off distance, separation speed and cleaning interval, with the responses being measurements of paste height and volume. Optimum screen-printer settings were determined which give adequate paste volume and height and a good print definition. The reflow experiment investigated the following parameters of the temperature profile: preheat, soak, peak and cool down temperatures, and conveyor speed. The resulting solder joints were evaluated using cross-section analysis and x-ray techniques in order to determine the presence of defects. A mechanical fatigue test was also carried out in order to compare the strength of the solder joints. The overall quality of the lead-free solder joints was determined from these tests and compared to that of tin-lead. The outcome is a set of manufacturing guidelines for transferring to lead-free solder including optimum screen-printer and reflow oven settings for use with an SnAgCu solder.

scholarly journals Analysis of Defects Generated by the Reflow Soldering in SMT (Surface Mount Technology) Assembly Applying the Six Sigma Method

2004 ◽  
Vol 1 (2) ◽  
pp. 17-25
Author(s):  
Ana C. Bueno ◽  
Maíra P. Shiki ◽  
Valdemir R. De Lima ◽  
Luis G. Brandão ◽  
Maurício M. Oka
Keyword(s):  
Six Sigma ◽  
Failure Modes ◽  
Solder Paste ◽  
Reflow Process ◽  
Reflow Time ◽  
Reflow Soldering ◽  
Effect Analysis ◽  
Soldering Process ◽  
Memory Modules ◽  
Edge Connector

The Six Sigma method using the DMAIC methodology is being applied for analyzing the reflow soldering process in an SMT assembly line. The Define phase (D) and Measure phase (M) were concluded, the Analysis (A) phase is being implemented, and the Improve (I) and Control (C) phases will be the next ones. Defects generated during the reflow process were classified and measured both on assembled memory modules and on virgin laminates that were passed through the oven during the reflow of these modules. Spots of solder and flux were found on the edge connector of the modules and also on the surface of the virgin laminates. It was found that these defects are generated inside the reflow oven, indicating that the oven is contaminated. Two solder pastes were analyzed and consequently, two temperature profiles were used. The amount of defects generated by the oven was found to be independent on the temperature profile. On the other hand the amount of defects depends on the solder paste that is used. The FMEA (Failure Mode and Effect Analysis) was also accomplished. As a result, the main failure modes of the reflow process were determined, namely, the heating rate, the soak temperature, the conveyor velocity, the reflow temperature, the reflow time, and the cooling rate.

Open Defects in PBGA Assembly Solder Joints

2003 ◽  
Vol 125 (1) ◽  
pp. 157-161 ◽  
Author(s):  
S. H. Fan ◽  
Y. C. Chan ◽  
J. K. L. Lai
Keyword(s):  
Solder Joint ◽  
Mechanism Analysis ◽  
Solder Paste ◽  
Soldering Process ◽  
Insufficient Amount ◽  
Solder Balls ◽  
Defect Mechanism ◽  
Open Defect ◽  
Very High ◽  
Thermal Stability Of

PBGA has the advantage of being compatible with existing surface-mount process. The eutectic solder balls collapse during reflow accommodates the lack of co-planarity, the surface tension between solder ball and associated pad creates a strong self-centering property to compensate for any placement offsets. However, some problems emerged in practice due to its special features. The major challenges for manufacturer are the inspection of solder joint and to perform touch-up. In most cases, the defect of solder joint cannot be found until in-circuit or functional testing is performed. At this stage, it becomes difficult to determine whether the defect is due to a solder joint or the component itself. Hence controlling the open defect is very important in the PBGA assembling process. It was found that three kinds of defective modes are responsible for the open defect; insufficient heating in the solder melting phase, poor thermal stability of PCB and PBGA and insufficient amount of printing solder paste. Based on the defect mechanism analysis, by optimizing the soldering process, very high assembly yield was achieved.

Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

2011 ◽  
Vol 2011 (1) ◽  
pp. 000953-000960 ◽  
Author(s):  
Thomas Oppert ◽  
Rainer Dohle ◽  
Jörg Franke ◽  
Stefan Härter
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Temperature Cycling ◽  
Solder Paste ◽  
Wafer Level ◽  
Solder Alloys ◽  
Flip Chips ◽  
Fine Pitch ◽  
Solder Bumps ◽  
Cost Efficient

The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process. To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide. The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1]. Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.

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