Equivalent Capacitance Approach to Calculate Effective Roughness Dielectric Parameters for Copper Foils on Printed Circuit Boards

2018 ◽  
Vol 15 (2) ◽  
pp. 49-62 ◽  
Author(s):  
Marina Y. Koledintseva ◽  
Tracey Vincent
Keyword(s):  
Transition Layer ◽  
Numerical Models ◽  
Thin Layers ◽  
Circuit Board ◽  
Dielectric Parameters ◽  
Printed Circuit ◽  
Copper Foils ◽  
Effective Roughness ◽  
Equivalent Capacitance ◽  
Gradual Variation

Effective roughness dielectric (ERD) is a homogeneous lossy dielectric layer of certain thickness with effective (averaged) dielectric parameters. The ERD layer is used to model copper foil roughness in printed circuit board interconnects by being placed on a smooth conductor surface to substitute an inhomogeneous transition layer between a conductor and laminate substrate dielectric. This work derives the ERD parameters based on the understanding that there is a gradual variation of concentration of metallic inclusions in the transition layer between the dielectric and foil. The gradual variation can be structured as thin layers that are obtained using the equivalent capacitance approach. The concentration profile is extracted from scanning electron microscopy or high-resolution optical microscopy. As the concentration of metallic particles increases along the axis normal to the laminate dielectric and foil boundary, two regions can be discerned: an insulating (prepercolation) region and a conducting (percolation) region. The rates of increase in effective loss (or corresponding conductivity) in these two regions differ significantly. The proposed model of equivalent capacitance with gradient dielectric is applied to a number of different types of copper foils. The frequency-dependent dielectric parameters of the homogenized ERD are calculated from the equivalent capacitance. The results are validated using 3D numerical electromagnetic simulations. There are two types of numerical models: with homogeneous ERD parameters and layered. Both models show excellent agreement with measurements.

Characteristics of Radiated Emission from a Printed Circuit Board with a Slit

2012 ◽  
Vol 132 (6) ◽  
pp. 404-410 ◽  
Author(s):  
Kenichi Nakayama ◽  
Kenichi Kagoshima ◽  
Shigeki Takeda
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Printed Circuit ◽  
Radiated Emission

Confirming the Signal Integrity in Transmission of Digital Signals on Microstrip Straight Circuits via the Eye Diagrams

2014 ◽  
Vol 5 (1) ◽  
pp. 737-741
Author(s):  
Alejandro Dueñas Jiménez ◽  
Francisco Jiménez Hernández
Keyword(s):  
Integrated Circuits ◽  
Printed Circuit Board ◽  
Signal Integrity ◽  
High Volume ◽  
Information Storage ◽  
Circuit Board ◽  
Electromagnetic Simulation ◽  
Electronic Systems ◽  
Digital Signals ◽  
Printed Circuit

Because of the high volume of processing, transmission, and information storage, electronic systems presently requires faster clock speeds tosynchronizethe integrated circuits. Presently the “speeds” on the connections of a printed circuit board (PCB) are in the order of the GHz. At these frequencies the behavior of the interconnects are more like that of a transmission line, and hence distortion, delay, and phase shift- effects caused by phenomena like cross talk, ringing and over shot are present and may be undesirable for the performance of a circuit or system.Some of these phrases were extracted from the chapter eight of book “2-D Electromagnetic Simulation of Passive Microstrip Circuits” from the corresponding author of this paper.

Root Cause Analysis of a Connector Time-Delayed Fracture

2015 ◽  
Author(s):  
Prabjit Singh ◽  
Ying Yu ◽  
Robert E. Davis
Keyword(s):  
Printed Circuit Board ◽  
Ceramic Substrate ◽  
Circuit Board ◽  
Delayed Fracture ◽  
Ceramic Substrates ◽  
Printed Circuit ◽  
Root Cause ◽  
Chip Carrier ◽  
Electrical Connections ◽  
Grain Boundary Grooves

Abstract A land-grid array connector, electrically connecting an array of plated contact pads on a ceramic substrate chip carrier to plated contact pads on a printed circuit board (PCB), failed in a year after assembly due to time-delayed fracture of multiple C-shaped spring connectors. The land-grid-array connectors analyzed had arrays of connectors consisting of gold on nickel plated Be-Cu C-shaped springs in compression that made electrical connections between the pads on the ceramic substrates and the PCBs. Metallography, fractography and surface analyses revealed the root cause of the C-spring connector fracture to be plating solutions trapped in deep grain boundary grooves etched into the C-spring connectors during the pre-plating cleaning operation. The stress necessary for the stress corrosion cracking mechanism was provided by the C-spring connectors, in the land-grid array, being compressed between the ceramic substrate and the printed circuit board.

Application of Lock-in Thermography on PCB for Fault Localization and Validation of Failure Mechanism Due to External Discrete Component Variation

2010 ◽  
Author(s):  
William Ng ◽  
Kevin Weaver ◽  
Zachary Gemmill ◽  
Herve Deslandes ◽  
Rudolf Schlangen
Keyword(s):  
Failure Mechanism ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Hot Spot ◽  
Circuit Board ◽  
Discrete Component ◽  
Printed Circuit ◽  
Thermal Signature ◽  
Lock In

Abstract This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.

Temperature and Humidity Dependent Reliability Analysis of RGB LED Chips

2006 ◽  
Author(s):  
Jun-Xian Fu ◽  
Shukri Souri ◽  
James S. Harris
Keyword(s):  
Reliability Analysis ◽  
Printed Circuit Board ◽  
Light Emitting Diode ◽  
Circuit Board ◽  
Light Emitting ◽  
Printed Circuit ◽  
Root Cause ◽  
Micro Cracks ◽  
Temperature And Humidity

Abstract Temperature and humidity dependent reliability analysis was performed based on a case study involving an indicator printed-circuit board with surface-mounted multiple-die red, green and blue light-emitting diode chips. Reported intermittent failures were investigated and the root cause was attributed to a non-optimized reflow process that resulted in micro-cracks and delaminations within the molding resin of the chips.

Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint

2004 ◽  
Author(s):  
Norman J. Armendariz ◽  
Prawin Paulraj
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Gold Surface ◽  
Circuit Board ◽  
Lead Free ◽  
Processing Temperature ◽  
The European Union ◽  
Printed Circuit ◽  
Higher Temperature ◽  
Tin Silver Copper

Abstract The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.

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