Proposal of Ultrafine and High Reliable Trench Wiring Process for Organic Interposer

2017 ◽  
Vol 14 (1) ◽  
pp. 26-31 ◽  
Author(s):  
Kazuyuki Mitsukura ◽  
Masaya Toba ◽  
Kousuke Urashima ◽  
Yoshinori Ejiri ◽  
Kenichi Iwashita ◽  
...  
Keyword(s):  
Laser Ablation ◽  
Seed Layer ◽  
High Reliability ◽  
Metal Layer ◽  
Stress Test ◽  
Side Wall ◽  
Moisture Sensitivity ◽  
Sintered Copper ◽  
Fine Resolution ◽  
Level 2

An organic interposer technology with ultrafine line and space is required to achieve high-density interconnection between chips. In this article, we propose a high reliability, ultrafine trench wiring process. Currently, trench wiring is made by laser ablation of dielectric, sputtering, copper plating, and then chemical mechanical polishing (CMP). However, it is challenging to achieve fine trench with smooth side wall using laser ablation, and CMP is also not suitable because of its high assembly cost. Reliability is another challenge because of the narrower and thinner insulator. We have developed a photosensitive insulation film (PIF) with fine resolution. The trench wiring of 2/2 μm line and space has been successfully assembled by photolithography, plating, and surface planer method as the alternative to CMP. The wiring layer of 2/2 μm line and space, which is covered with a thin barrier metal layer and PIF, has passed the biased highly accelerated temperature and humidity stress test (HAST) screening. A copper paste is applied as a seed layer instead of sputtering. The sintered copper filled with adhesive paste into the copper pores is compatible as the seed layer, and the wiring layer of 10/10 μm line and space has passed the reliability tests such as moisture sensitivity level 2 (MSL2), thermal cycling test, and biased HAST.

Proposal of Ultra-fine and High Reliable Trench Wiring Process for Organic Interposer

2016 ◽  
Vol 2016 (1) ◽  
pp. 000165-000170 ◽  
Author(s):  
Kazuyuki Mitsukura ◽  
Masaya Toba ◽  
Kousuke Urashima ◽  
Yoshinori Ejiri ◽  
Kenichi Iwashita ◽  
...  
Keyword(s):  
Laser Ablation ◽  
Seed Layer ◽  
High Reliability ◽  
Metal Layer ◽  
Stress Test ◽  
Side Wall ◽  
Sintered Copper ◽  
Barrier Metal ◽  
Fine Resolution ◽  
Thin Barrier

Abstract An organic interposer technology with ultra-fine line and space is required in order to achieve high density interconnection between chips. In this paper we propose a high reliability, ultra-fine trench wiring process. Current trench wiring is made by laser ablation of dielectric, spattering, copper plating and then Chemical mechanical polishing (CMP). However, it is challenging for laser ablation to achieve fine trench with smooth side wall and CMP is not suitable because of high assembly cost. Reliability is another challenge because of the narrower and thinner insulator. We have developed photosensitive insulation film (PIF) with fine resolution. The trench wiring of 2/2 μm line and space has been successfully assembled by photolithography, plating and surface planer method as the alternative to CMP. The wiring layer of 2/2 μm line and space, which was covered with the thin barrier metal layer and PIF, has passed the biased highly accelerated temperature and humidity stress test (HAST) screening. In addition to the above process a copper paste has been applied as a seed layer instead of the spattering. The sintered copper filled with adhesive paste into the copper porous is compatible as the seed layer and the wiring layer of 10/10 μm line and space has passed the reliability tests such as MSL2, thermal cycling test and biased HAST.

Highly Reliable Cu Wiring Layer of 1/1 μm Line/Space Using Newly Designed Insulation Barrier Film

2017 ◽  
Vol 2017 (1) ◽  
pp. 000140-000145 ◽  
Author(s):  
Kazuyuki Mitsukura ◽  
Shinichiro Abe ◽  
Masaya Toba ◽  
Tomonori Minegishi ◽  
Kazuhiko Kurafuchi
Keyword(s):  
Low Cost ◽  
Stress Test ◽  
Chloride Ion ◽  
Moisture Sensitivity ◽  
Sensitivity Level ◽  
Accelerated Stress Test ◽  
Good Adhesive ◽  
Line Space ◽  
Level 2 ◽  
Barrier Film

Abstract The interposer or fan-out packaging technology with ultra-fine line/space has been required in order to achieve high density interconnection between chips with low cost. In this paper, we propose the iBF (insulation barrier film) to satisfy the insulation reliability of 1/1 μm ultra-fine trench wiring. The features of iBF are very low moisture absorptivity less than 0.3%, chloride ion impurities less than 1.0 ppm and high resistance to hydrolysis. In addition, iBF has good adhesive strength to Ti and Cu. The trench wiring was fabricated for mechanical and insulation reliability evaluation using photosensitive dielectric, then covered with iBF. The obtained trench wiring with 2/2, 1.5/1.5 and 1/1 μm line/space has passed the reliability tests such as moisture sensitivity level 2, thermal cycling test and biased HAST (highly accelerated stress test). We have also verified high resolution of photosensitive dielectric and fabrication of ultra-fine trench wiring on iBF to realize fine multi-layer wiring.

Investigation of High Frequency Failures on a 0.35μm CMOS IC

1999 ◽  
Author(s):  
Alan Kennen ◽  
John F. Guravage ◽  
Lauren Foster ◽  
John Kornblum
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Integrated Circuit ◽  
Metal Layer ◽  
Ion Beam ◽  
Stress Test ◽  
Design For Test ◽  
Interface Failure ◽  
Serial Interface ◽  
High Impedance

Abstract Rapidly changing technology highlights the necessity of developing new failure analysis methodologies. This paper will discuss the combination of two techniques, Design for Test (DFT) and Focused Ion Beam (FIB) analysis, as a means for successfully isolating and identifying a series of high impedance failure sites in a 0.35 μm CMOS design. Although DFT was designed for production testing, the failure mechanism discussed in this paper may not have been isolated without this technique. The device of interest is a mixed signal integrated circuit that provides a digital up-convert function and quadrature modulation. The majority of the circuit functions are digital and as such the majority of the die area is digital. For this analysis, Built In Self Test (BIST) circuitry, an evaluation board for bench testing and FIB techniques were used to successfully identify an unusual failure mechanism. Samples were subjected to Highly Accelerated Stress Test (HAST) as part of the device qualification effort. Post-HAST electrical testing at 200MHz indicated that two units were non-functional. Several different functional blocks on the chip failed electrical testing. One part of the circuitry that failed was the serial interface. The failure analysis team decided to look at the serial interface failure mode first because of the simplicity of the test. After thorough analysis the FA team discovered increasing the data setup time at the serial port input allowed the device to work properly. SEM and FIB techniques were performed which identified a high impedance connection between a metal layer and the underlying via layer. The circuit was modified using a FIB edit, after which all vectors were read back correctly, without the additional set-up time.

A 300°C High Reliability HALT/HAST Screening/Sorting Procedure for Ceramic Capacitors

2018 ◽  
Vol 2018 (HiTEC) ◽  
pp. 000129-000137 ◽  
Author(s):  
Harold L. Snyder
Keyword(s):  
High Reliability ◽  
Stress Test ◽  
Electrical Current ◽  
Accelerated Life Test ◽  
Test Results ◽  
Electrical Model ◽  
Current Leakage ◽  
Ceramic Capacitor ◽  
Ceramic Capacitors ◽  
Before And After

Abstract A highly accelerated life test (HALT) and highly accelerated stress test (HAST) procedure for ceramic capacitors developed by the author in the mid 1980's to early 1990's, and published in 1994, consists of a 400 Volt biased six (6) hour stress sort at 150°C (423K), a methanol current leakage test that located mechanical and structural cracks, a visual inspection at ten times (10×) magnification, and a capacitance and dissipation measurement before and after the test. In over thirty (30) years of use, there has never been a user reported in-circuit failure in industrial, military, and aerospace application at temperatures as high as 500°C (773K). However, reviewing user feedback, two concerns with the original sorting procedure are the stress is performed at 150°C (423K), and the lack of a more detailed ceramic capacitor electrical model. To address the first, the low aging temperature, the stress temperature was increased from 150°C to 300°C, in order to age ceramic solid state crystal mineral phases that may change with temperature. The test results for X7R and NP0/COG multilayer ceramic capacitors (MLCC) at 300°C, are compared to the test results using the original HALT/HAST procedure at 150°C. Differences between X7R/NP0/COG and porcelain capacitors are discussed when applicable. Further, a more detailed ceramic capacitor electrical model that represents the physical and electrical characteristics of the ceramic capacitors is presented, including the electrical current leakage effects with temperature, and the carbonized residue effects from the manufacturing process.

scholarly journals Copper Light-induced Plating Contacts with Ni Seed-layer for mc-Si Solar Cells after Laser Ablation of SiNx:H

2013 ◽  
Vol 38 ◽  
pp. 713-719 ◽  
Author(s):  
Alexandru Focsa ◽  
Daniele Blanc ◽  
Gilles Poulain ◽  
Corina Barbos ◽  
Michel Gauthier ◽  
...  
Keyword(s):  
Solar Cells ◽  
Laser Ablation ◽  
Seed Layer ◽  
Si Solar Cells ◽  
Light Induced Plating

Towards an improved understanding of high-resolution impurity signals in deep Antarctic ice cores

2020 ◽  
Author(s):  
Pascal Bohleber ◽  
Marco Roman ◽  
Carlo Barbante ◽  
Barbara Stenni ◽  
Barbara Delmonte
Keyword(s):  
Laser Ablation ◽  
High Resolution ◽  
Inductively Coupled Plasma ◽  
Ice Core ◽  
Ice Cores ◽  
Inductively Coupled ◽  
Icp Ms ◽  
First Results ◽  
Plasma Mass Spectrometry ◽  
Fine Resolution

<p>Laser ablation inductively coupled plasma mass spectrometry (LA-ICP-MS) offers minimally destructive ice core impurity analysis at micron-scale resolution. This technique is especially suited for exploring closely spaced layers of ice within samples collected at low accumulation sites or in regions of highly compressed and thinned ice. Accordingly, LA-ICP-MS promises invaluable insights in the analysis of a future “Oldest ice core” from Antarctica. However, in contrast to ice core melting techniques, taking into account the location of impurities is crucial to avoid misinterpretation of ultra-fine resolution signals obtained from newly emerging laser ablation technologies. Here we present first results from a new LA-ICP-MS setup developed at the University of Venice, based on a customized two-volume cryogenic ablation chamber optimized for fast wash-out times. We apply our method for high-resolution chemical imagining analysis of impurities in samples from intermediate and deep sections of the Talos Dome and EPICA Dome C ice cores. We discuss the localization of both soluble and insoluble impurities within the ice matrix and evaluate the spatial significance of a single profile along the main core axis. With this, we aim at establishing a firm basis for a future deployment of the LA-ICP-MS in an “Oldest Ice Core”. Moreover, our work illustrates how LA-ICP-MS may offer new means to study the impurity-microstructure interplay in deep polar ice, thereby promising to advance our understanding of these fundamental processes.</p>

Validity and Reliability of the Huet Questionnaire to Assess Maximal Oxygen Uptake

2004 ◽  
Vol 29 (5) ◽  
pp. 623-638 ◽  
Author(s):  
Damien Trivel ◽  
Paul Calmels ◽  
Luc Léger ◽  
Thierry Busso ◽  
Xavier Devillard ◽  
...  
Keyword(s):  
Oxygen Uptake ◽  
Maximal Oxygen Uptake ◽  
High Reliability ◽  
Stress Test ◽  
Intraclass Correlation ◽  
Correlation Coefficients ◽  
Epidemiological Studies ◽  
Cycle Ergometer ◽  
Sample Population ◽  
Validity And Reliability

The usual fitness tests available to assess maximal oxygen uptake [Formula: see text] a key fitness component, are not particularly useful for epidemiological studies. Questionnaires to assess [Formula: see text] however, are simple, easy to use, and inexpensive. In 1986, Huet developed such a French general questionnaire, which now also has an English version. Its simplicity is interesting as it could be used to survey large populations. The purpose of this study was to assess the validity and reliability of this Huet questionnaire in a sample of healthy French volunteers. A total of 108 subjects were included in this study, 88 males and 20 females. The validity of the questionnaire was checked using correlation coefficients and a Bland-Altman plot between questionnaire estimations and measures of [Formula: see text] obtained with a stress test on a cycle ergometer. An intraclass correlation coefficient (ICC) was also calculated to determine the reliability of the questionnaire. Significant correlation was obtained with the Huet questionnaire and measured [Formula: see text] (r2 = 0.77, p = 0.0001, SEE = 5.97 ml•kg−1•min−1, n = 108). The ICC showed very high reliability (ICC = 0.988, n = 21). The Huet questionnaire is an easy, rapidly administered tool that correlated highly with [Formula: see text] in this sample population. Key words: physical activity, epidemiology, evaluation

scholarly journals Improvement on Fully Filled Through Silicon Vias by Optimized Sputtering and Electroplating Conditions

Materials ◽  
2019 ◽  
Vol 12 (22) ◽  
pp. 3713 ◽  
Author(s):  
Fei Zhao
Keyword(s):  
Electron Microscope ◽  
Integrated Circuit ◽  
Seed Layer ◽  
High Reliability ◽  
Through Silicon Vias ◽  
X Ray ◽  
Layer Structures ◽  
Silicon Vias ◽  
Scanning Electron

The high reliability of electroplating through silicon vias (TSVs) is an attractive hotspot in the application of high-density integrated circuit packaging. In this paper, improvements for fully filled TSVs by optimizing sputtering and electroplating conditions were introduced. Particular attention was paid to the samples with different seed layer structures. These samples were fabricated by different sputtering and treatment approaches, and accompanied with various electroplating profile adjustments. The images were observed and characterized by X-ray equipment and a scanning electron microscope (SEM). The results show that optimized sputtering and electroplating conditions can help improve the quality of TSVs, which could be interpreted as the interface effect of the TSV structure.

A 300°C High Reliability HALT/HAST Screening/Sorting Procedure for Ceramic Capacitors – Part 2

2021 ◽  
Vol 2021 (HiTEC) ◽  
pp. 000094-000099
Author(s):  
Harold L. Snyder
Keyword(s):  
High Reliability ◽  
Stress Test ◽  
Electrical Current ◽  
Accelerated Life Test ◽  
Test Results ◽  
Electrical Model ◽  
Current Leakage ◽  
Ceramic Capacitor ◽  
Ceramic Capacitors ◽  
Before And After

Abstract This is Part 2 of a study initially presented at HiTEC 2018, for context, some introductory material is duplicated. A highly accelerated life test (HALT) and highly accelerated stress test (HAST) procedure for ceramic capacitors developed by the author in the mid 1980’s to early 1990’s, and published in 1994, consists of a 400 Volt biased six (6) hour stress sort at 150°C (423K), a methanol current leakage test that located mechanical and structural cracks, a visual inspection at ten times (10X) magnification, and a capacitance and dissipation measurement before and after the test. In over thirty (30) years of use, there has never been a user reported in-circuit failure in industrial, military, and aerospace application at temperatures as high as 500°C (773K). However, reviewing user feedback, two concerns with the original sorting procedure are the stress is performed at 150°C (423K), and the lack of a more detailed ceramic capacitor electrical model. To address the first, the low aging temperature, the stress temperature was increased from 150°C to 300°C, in order to age ceramic solid state crystal mineral phases that may change with temperature. The test results for X7R and NP0/COG multilayer ceramic capacitors (MLCC) at 300°C, are compared to the test results using the original HALT/HAST procedure at 150°C. Differences between X7R/NP0/COG and porcelain capacitors are discussed when applicable. Further, a more detailed ceramic capacitor electrical model that represents the physical and electrical characteristics of the ceramic capacitors is presented, including the electrical current leakage effects with temperature, and the carbonized residue effects from the manufacturing process.

Investigation of Forward Voltage Degradation due to Process-Induced Defects in 4H-SiC MOSFET

2018 ◽  
Vol 924 ◽  
pp. 365-368 ◽  
Author(s):  
Kumiko Konishi ◽  
Ryusei Fujita ◽  
Yuki Mori ◽  
Akio Shima
Keyword(s):  
High Reliability ◽  
Stress Test ◽  
Implantation Dose ◽  
Imaging Method ◽  
Stress Tests ◽  
Forward Voltage ◽  
Current Stress ◽  
Before And After ◽  
Induced Defects ◽  
Voltage Degradation

We investigated process induced defects at various ion implantation conditions, and evaluated forward voltage degradation of body diode in 3.3 kV SiC MOSFET. First, by using photoluminescence (PL) observation, we evaluated the formation level of Basal Plane Dislocations (BPD) induced by Al implantation and anneal process with various Al implantation dose. Second, 3.3 kV double-diffused SiC MOSFETs were fabricated and forward current stress tests were performed to body diodes in SiC MOSFETs. Then, electrical characteristics of SiC MOSFETs before and after the stress test were measured, and expanded Stacking faults (SFs) in SiC epitaxial layer after the stress test were observed by PL imaging method. These results indicate that low dose or high temperature Al implantation conditions can suppress the formation of BPDs, and SiC MOSFETs fabricated using optimized Al implantation conditions show high reliability under current stress test.

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