Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300 mm Multi-Project Wafer (MPW)

2011 ◽  
Vol 8 (4) ◽  
pp. 171-178 ◽  
Author(s):  
J. H. Lau ◽  
C.-J. Zhan ◽  
P.-J. Tzeng ◽  
C.-K. Lee ◽  
M.-J. Dai ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Organic Substrate ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
3D Ic ◽  
Solder Bumps ◽  
Bottom Side ◽  
Free Solder ◽  
Key Enabling Technologies

The feasibility of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) interposer with an RDL (redistribution layer) on both sides, IPD (integrated passive devices), and SS (stress sensors). This interposer is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and is then overmolded on its top side for pick and place purposes. The interposer's bottom side is attached to an organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). Key enabling technologies such as TSV etching, chemical mechanical polishing (CMP), thin-wafer handling, thermal management, and microbumping, assembly, and reliability are highlighted.

Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW)

2011 ◽  
Vol 2011 (1) ◽  
pp. 000446-000454
Author(s):  
J. H. Lau ◽  
C-J Zhan ◽  
P-J Tzeng ◽  
C-K Lee ◽  
M-J Dai ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Organic Substrate ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
3D Ic ◽  
Solder Bumps ◽  
Bottom Side ◽  
Free Solder ◽  
Key Enabling Technologies

The feasibility of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) interposer with RDL (redistribution layer) on both sides, IPD (integrated passive devices) and SS (stress sensors). This interposer is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and then overmolded on its top side for pick and place purposes. The interposer’s bottom-side is attached to an organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). Key enabling technologies such as TSV etching, chemical mechanical polishing (CMP), thin-wafer handling, thermal management, and microbumping, assembly and reliability are highlighted.

Large Size Silicon Interposer and 3D IC Integration for System-in-Packaging (SiP)

2012 ◽  
Vol 2012 (1) ◽  
pp. 001209-001214 ◽  
Author(s):  
John Lau ◽  
Pei-Jer Tzeng ◽  
Chau-Jie Zhan ◽  
Ching-Kuan Lee ◽  
Ming-Ji Dai ◽  
...  
Keyword(s):  
Feasibility Study ◽  
Organic Substrate ◽  
Lead Free ◽  
Lead Free Solder ◽  
3D Ic ◽  
Through Silicon Via ◽  
Large Size ◽  
Solder Bumps ◽  
Bottom Side ◽  
Free Solder

The feasibility study of a 3D IC integration SiP is demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) passive interposer (28mm × 28mm) with double sided wiring layers. This interposer is used to support a very large chip (22mm × 18mm) on its top-side and 2 smaller chips (10mm × 10mm) at its bottom-side (a truly 3D IC integration). The bottom side of this interposer is attached to an organic substrate (40mm × 40mm) (with ordinary lead-free solder bumps). The lead-free micro solder bumps (Cu/Sn) on all the chips are made by wafer bumping with a UBM (under bump metallurgy) of Ti/Cu and the bump structure of Cu and Sn.

Site Redressing Techniques and Rework of Lead-Free Chip Scale Packages

2003 ◽  
Author(s):  
Arun Gowda ◽  
Anthony Primavera ◽  
K. Srihari
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Printed Circuit ◽  
Free Solder ◽  
The Individual ◽  
Component Assembly ◽  
Free Area

The implementation of lead-free solder into an electronics assembly process necessitates the reassessment of the individual factors involved in component attachment and rework. A component assembly undergoes multiple thermal cycles during rework. With the use of lead-free solder, the assemblies are subjected to higher assembly and rework temperatures than those required for eutectic tin-lead assemblies. The rework of lead-free area array components involves the removal of defective component, preparation of the printed circuit board attachment pad (site redressing), solder paste replenishment or flux deposition, and component placement and reflow. This paper primarily focuses on the site redressing aspect of lead-free rework, followed by the development of rework processes for lead-free chip scale packages utilizing the knowledge gained in the site redressing studies.

Failure Analysis Techniques for Lead-Free Solder Joints

2005 ◽  
Author(s):  
Todd Castello ◽  
Dan Rooney ◽  
Dongkai Shangguan
Keyword(s):  
Failure Analysis ◽  
Printed Circuit Board ◽  
Failure Modes ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Printed Circuit Board Assembly ◽  
Analysis Techniques ◽  
Solder Interconnects ◽  
Free Solder

Abstract Printed circuit board assembly with lead free solder is now a reality for most global electronics manufacturers. Extensive research and development has been conducted to bring lead free assembly processes to a demonstrated proficiency. Failure analysis has been an integral part of this effort and will continue to be needed to solve problems in volume production. Many failure analysis techniques can be directly applied to study lead free solder interconnects, while others may require some modification in order to provide adequate analysis results. In this paper, several of the most commonly applied techniques for solder joint failure analysis will be reviewed, including visual inspection, x-ray radiography, mechanical strength testing, dye & pry, metallography, and microscopy/photomicrography, comparing their application to lead bearing and lead free solder interconnects. Common failure modes and mechanisms will be described with examples specific to lead free solders, following PCB assembly as well as after accelerated reliability tests.

Creep Analysis of Wafer Level Chip Scale Package (WLCSP) With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints and Microvia Build-Up Printed Circuit Board

2000 ◽  
Author(s):  
John H. Lau ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Shear Stress ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Wafer Level ◽  
Shear Creep ◽  
Printed Circuit ◽  
Chip Scale Package ◽  
Free Solder

Abstract In this study, time-temperature-dependent nonlinear analyses of lead-free solder bumped wafer level chip scale package (WLCSP) on printed circuit board (PCB) assemblies subjected to thermal cycling conditions are presented. Two different lead-free solder alloys are considered, namely, 96.5wt%Sn-3.5wt%Ag and 100wt%In. The 62wt%Sn-36wt%Pb-2wt%Ag solder alloy is also considered to establish a baseline. All of these solder alloys are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The shear stress and shear creep strain hysteresis loops, shear stress history, and shear creep strain history at the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of lead-free solder bumped WLCSP on PCB assemblies. Also, the effects of microvia build-up PCB on the WLCSP solder joint reliability are investigated.

Wafer Bumping and Characterizations of Fine-Pitch Lead-Free Solder Microbumps on 12” (300mm) wafer for 3D IC Integration

2011 ◽  
Vol 2011 (1) ◽  
pp. 000650-000656
Author(s):  
J. H. Lau ◽  
P-J Tzeng ◽  
C-K Lee ◽  
C-J Zhan ◽  
M-J Dai ◽  
...  
Keyword(s):  
Cross Sections ◽  
Lead Free ◽  
Lead Free Solder ◽  
Sem Images ◽  
3D Ic ◽  
Fine Pitch ◽  
Solder Bumps ◽  
Before And After ◽  
Free Solder

In this study, the wafer bumping and characterization of fine-pitch lead-free solder microbumps on 300mm wafer for 3D IC integration are investigated. Emphasis is placed on the Cu-plating solutions (conformal and bottom-up). Also, the amount of Cu and solder (Sn) volumes is examined. Furthermore, characterizations such as shearing test and aging of the microbumps are provided and cross sections/SEM images of the microbumps before and after test are discussed. Finally, the process windows of applying the conventional electroplating wafer bumping method of the ordinary solder bumps to the microbumps are also presented.

Study of immersion silver and tin printed-circuit-board surface finishes in lead-free solder applications

2004 ◽  
Vol 33 (9) ◽  
pp. 977-990 ◽  
Author(s):  
Minna Arra ◽  
Dongkai Shangguan ◽  
Dongji Xie ◽  
Janne Sundelin ◽  
Toivo Lepistö ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Printed Circuit ◽  
Surface Finishes ◽  
Board Surface ◽  
Free Solder ◽  
Immersion Silver
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