RF Modules (Tx–Rx) with Multifunctional MMICs

2017 ◽  
Vol 2017 (NOR) ◽  
pp. 1-5
Author(s):  
Martin Oppermann ◽  
Ralf Rieger
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Next Generation ◽  
Electronic Warfare ◽  
Chip Area ◽  
Operating Modes ◽  
Half Wavelength ◽  
X Band ◽  
Physical Channel ◽  
Promising Solution

Abstract Next generation RF sensor modules for multifunction active electronically steered antenna (AESA) systems will need a combination of different operating modes, such as radar, electronic warfare (EW) functionalities and communications/datalinks within the same antenna frontend. They typically operate in C-Band, X-Band and Ku-Band and imply a bandwidth requirement of more than 10 GHz. For the realisation of modern active electronically steered antennas, the transmit/receive (T/R) modules have to match strict geometry demands. A major challenge for these future multifunction RF sensor modules is dictated by the half-wavelength antenna grid spacing, that limits the physical channel width to < 12 mm or even less, depending on the highest frequency of operation with accordant beam pointing requirements. A promising solution to overcome these geometry demands is the reduction of the total monolithic microwave integrated circuit (MMIC) chip area, achieved by integrating individual RF functionalities, which are commonly achieved through individual integrated circuits (ICs), into new multifunctional (MFC) MMICs. Various concepts, some of them already implemented, towards next generation RF sensor modules will be discussed and explained in this work.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

scholarly journals Design and Implementation of Ternary Logic Integrated Circuits by Using Novel Two-Dimensional Materials

2019 ◽  
Vol 9 (20) ◽  
pp. 4212 ◽  
Author(s):  
Mingqiang Huang ◽  
Xingli Wang ◽  
Guangchao Zhao ◽  
Philippe Coquet ◽  
Bengkang Tay
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Large Scale ◽  
2D Materials ◽  
Two Dimensional ◽  
Ternary Logic ◽  
Chip Area ◽  
Logic Devices ◽  
Ripple Carry Adder ◽  
Data Density

With the approaching end of Moore’s Law (that the number of transistors in a dense integrated circuit doubles every two years), the logic data density in modern binary digital integrated circuits can hardly be further improved due to the physical limitation. In this aspect, ternary logic (0, 1, 2) is a promising substitute to binary (0, 1) because of its higher number of logic states. In this work, we carry out a systematical study on the emerging two-dimensional (2D) materials (MoS2 and Black Phosphorus)-based ternary logic from individual ternary logic devices to large scale ternary integrated circuits. Various ternary logic devices, including the standard ternary inverter (STI), negative ternary inverter (NTI), positive ternary inverter (PTI) and especially the ternary decrement cycling inverter (DCI), have been successfully implemented using the 2D materials. Then, by taking advantage of the optimized ternary adder algorithm and the novel ternary cycling inverter, we design a novel ternary ripple-carry adder with great circuitry simplicity. Our design shows about a 50% reduction in the required number of transistors compared to the existing ternary technology. This work paves a new way for the ternary integrated circuits design, and shows potential to fulfill higher logic data density and a smaller chip area in the future.

scholarly journals Covert Gates: Protecting Integrated Circuits with Undetectable Camouflaging

2019 ◽  
pp. 86-118
Author(s):  
Bicky Shakya ◽  
Haoting Shen ◽  
Mark Tehranipoor ◽  
Domenic Forte
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Boolean Functions ◽  
Imaging Techniques ◽  
Security Analysis ◽  
Vlsi Testing ◽  
Non Invasive ◽  
Standard Cells ◽  
High Area ◽  
Promising Solution

Integrated circuit (IC) camouflaging has emerged as a promising solution for protecting semiconductor intellectual property (IP) against reverse engineering. Existing methods of camouflaging are based on standard cells that can assume one of many Boolean functions, either through variation of transistor threshold voltage or contact configurations. Unfortunately, such methods lead to high area, delay and power overheads, and are vulnerable to invasive as well as non-invasive attacks based on Boolean satisfiability/VLSI testing. In this paper, we propose, fabricate, and demonstrate a new cell camouflaging strategy, termed as ‘covert gate’ that leverages doping and dummy contacts to create camouflaged cells that are indistinguishable from regular standard cells under modern imaging techniques. We perform a comprehensive security analysis of covert gate, and show that it achieves high resiliency against SAT and test-based attacks at very low overheads. We also derive models to characterize the covert cells, and develop measures to incorporate them into a gate-level design. Simulation results of overheads and attacks are presented on benchmark circuits.

Research the load capacity of microcircuits

2020 ◽  
Vol 23 (3) ◽  
pp. 74-81
Author(s):  
Katerina S. Yarantseva ◽  
Gennady P. Shopin ◽  
Mikhail N. Piganov ◽  
Vladimir S. Andrusenko
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Pulse Generator ◽  
Load Capacity ◽  
Rectangular Pulse ◽  
Voltage Reference ◽  
Pulse Counter ◽  
Operating Modes ◽  
Low Levels ◽  
Definition Of

The device for the definition of the integrated circuits load-driving capability is offered. Device for determining the output capability of microcircuits refers to the field of microminiaturization and the technology of radio electronic equipment and can be used to control the parameters of microcircuits during their production. The device contains a rectangular pulse generator, an integrated circuit that is being tested, a repeater, load, a switch, an AND gate, a comparator, a pulse counter and a voltage reference, a vibrator, a reversible pulse counter, a decoder, and an indicator. Technical result when implementing the disclosed solution is high accuracy and reliability of determining load capacity of microcircuits. The proposed device allows increasing accuracy and reliability of defining circuits load-driving capacity. It also allows testing of TTL, Schottky-TTL, and MOSFET circuits. There are two switchable operating modes for testing fan-out for logical high and low levels. It is easy to replace a circuit that is being tested and load.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

Micromechanics Measurements Applied to Integrated Circuit Microelectronics

1997 ◽  
Vol 473 ◽  
Author(s):  
David R. Clarke
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Fracture Resistance ◽  
Interface Fracture ◽  
New Techniques ◽  
Fracture Properties ◽  
Engineered Structures ◽  
Mechanical And Fracture Properties ◽  
Interconnect Lines ◽  
Metallic Interconnect

ABSTRACTAs in other engineered structures, fracture occasionally occurs in integrated microelectronic circuits. Fracture can take a number of forms including voiding of metallic interconnect lines, decohesion of interfaces, and stress-induced microcracking of thin films. The characteristic feature that distinguishes such fracture phenomena from similar behaviors in other engineered structures is the length scales involved, typically micron and sub-micron. This length scale necessitates new techniques for measuring mechanical and fracture properties. In this work, we describe non-contact optical techniques for probing strains and a microscopic “decohesion” test for measuring interface fracture resistance in integrated circuits.

Nanofabricated SiO2-Si-SiO2 Resonant Tunneling Diodes

2000 ◽  
Vol 631 ◽  
Author(s):  
J. G. Fleming ◽  
E. Chow ◽  
S.-Y. Lin
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Resonant Tunneling ◽  
Resonant Tunneling Diodes ◽  
Resonance Tunneling ◽  
Tunneling Diodes

ABSTRACTResonance Tunneling Diodes (RTDs) are devices that can demonstrate very highspeed operation. Typically they have been fabricated using epitaxial techniques and materials not consistent with standard commercial integrated circuits. We report here the first demonstration of SiO2-Si-SiO2 RTDs. These new structures were fabricated using novel combinations of silicon integrated circuit processes.

The Radio Probe™: A New Measurement Tool for High Speed Integrated Circuits

2005 ◽  
Author(s):  
Mark Kimball
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Attenuation Factor ◽  
Cost Effective ◽  
Frequency Measurement ◽  
Single Frequency ◽  
Measurement Tool ◽  
Probe Design ◽  
Differential Measurement

Abstract This article presents a novel tool designed to allow circuit node measurements in a radio frequency (RF) integrated circuit. The discussion covers RF circuit problems; provides details on the Radio Probe design, which achieves an input impedance of 50Kohms and an overall attenuation factor of 0 dB; and describes signal to noise issues in the output signal, along with their improvement techniques. This cost-effective solution incorporates features that make it well suited to the task of differential measurement of circuit nodes within an RF IC. The Radio Probe concept offers a number of advantages compared to active probes. It is a single frequency measurement tool, so it complements, rather than replaces, active probes.

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