TCB Process Options to Achieve the Lowest Cost

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001277-001301
Author(s):  
Tom Strothmann

Thermocompression bonding enables the next generation fine pitch, 2.5D and 3D assembly technologies using Cu pillar interconnects, but to achieve widespread adoption the cost of TCB must become competitive with mass reflow processes. Stacked memory products drive the commercial volume today using TSV structures and TCB since it is the only technology able to achieve the desired stacked die construction and improved performance, but reducing the cost of assembly is still a key goal for those suppliers. In non-memory applications the choice of TCB can be driven by the bump pitch of the device or the requirement to control warpage of large die on laminate during assembly, but cost is still a key factor in the decision. The cost of a TCB process is largely driven by the UPH of the process where cost calculations are based on the cost per unit of material produced. As the UPH of a TCB process approaches 1400, the differential cost of the TCB process as compared to mass reflow becomes negligible. In the choice of a potential TCB process, special attention must be given to those processes that enable the highest UPH and the lowest cost. Processes used for TCB today can be grouped into two main categories; processes that use a pre-applied underfill and those that apply underfill after the bonding process. Underfills applied prior to bonding can be in the form of a non-conductive paste (TC-NCP) applied to a substrate or a non-conductive film applied to the wafer before dicing (TC-NCF). If underfill is applied after the bonding process, it is done as a Capillary Underfill (TC-CUF). In this case the die is underfilled in much the same way as in standard flip chip processes, but the process can be more challenging because of flux cleaning requirements and the narrower bondline of a typical TCB device. UPH is primarily driven by two factors; the range of temperature required by the bond head and the temperature ramp rate of the bond head. A process with less temperature range will have higher UPH and bond heads designed for the fastest cooling and heating rates will provide higher UPH processes. Two process options have been developed to minimize the temperature excursions required by the bond head and maximize the throughput. TC- NCF processes targeting stacked die and interposer products have been developed with throughputs approaching 2000 UPH. Substrate flux TC-CUF processes targeting assembly on laminate have been developed with throughputs that approach 2500 UPH. These two processes are expected to dominate TCB volume production moving forward as TCB enters mainstream production. This presentation will describe the methods used to achieve high throughput for both processes and the product application space appropriate for each one.

1991 ◽  
Vol 246 ◽  
Author(s):  
Ir. J. Van Humbeeck

AbstractA more systematic marketing research approach has finally revealed good ideas anticipating a market need for the use of shape memory alloys. The success of those new ideas, prototypes and applications are analysed in terms of “the value of the function”, defined as the importance of the function divided by the cost of providing the function. A high importance and/or a low cost of the function are thus the basic requirements for the successful introduction of shape memory applications. Attention is also paid to the way how the 4 P's, product, price, place, promotion (the marketing mix) are applied by the European companies. Those different items will be illustrated on the basis of some small-, medium- and largescale applications, used in different markets. “to the point research”, fundamental and applied, on material properties as well as on manufacturing (cost reduction) is being discussed as the key factor to increase the function value.


Author(s):  
Thomas Leneke ◽  
Soeren Hirsch ◽  
Bertram Schmidt

A key factor for the propagation of technological applications is the miniaturization of respective components, subsystems and overall systems. To meet future requirements in such size decreasing environments the packaging and mounting technology needs new impulses. 3D-MIDs (three-dimensional molded interconnect devices) exhibit a high potential for smart packages and assemblies. A three-dimensional shaped circuit carrier allows the integration of various functional features (e.g. electrical connections, housing, thermal management, mechanical support). This combination makes a further system shrinking possible. Yet, the mounting of high-density area-array fine-pitch packaged semiconductors (BGA, CSP, MCM) or bare dies to 3D-MIDs is problematic. The lack of a three-dimensional multilayer technology makes a collision free escape routing for devices with a high I/O count difficult. Therefore a new 3D-MID multilayer process was developed and combined with an established 3D-MID metallization process. A demonstrator with three metallization layers, capable, e.g., for flip-chip mounting of area-array packages, is fabricated. The multilayer structure of the demonstrator is investigated with respect to the mechanical and electrical behavior.


2000 ◽  
Vol 631 ◽  
Author(s):  
Thomas W. Crowe ◽  
Jeffrey L. Hesler ◽  
William L. Bishop ◽  
Willie E. Bowen ◽  
Richard F. Bradley ◽  
...  

ABSTRACTGaAs Schottky barrier diodes remain a workhorse technology for submillimeter-wave applications including radio astronomy, chemical spectroscopy, atmospheric studies, plasma diagnostics and compact range radar. This is because of the inherent speed of these devices and their ability to operate at room temperature. Although planar (flip-chip and beam-lead) diodes are replacing whisker contacted diodes throughout this frequency range, the handling and placement of such small GaAs chips limits performance and greatly increases component costs. Through the use of a novel wafer bonding process we have fabricated and tested submillimeter-wave components where the GaAs diode is integrated on a quartz substrate along with other circuit elements such as filters, probes and bias lines. This not only eliminates the cost of handling microscopically small chips, but also improves circuit performance. This is because the parasitic capacitance is reduced by the elimination of the GaAs substrate and the electrical embedding impedance seen by the diodes is more precisely controlled. Our wafer bonding process has been demonstrated through the fabrication and testing of a fundamental mixer at 585 GHz (Tmix < 1200K) and a 380 GHz subharmonically pumped mixer (Tmix < 1000K). This paper reviews the wafer bonding process and discusses how it can be used to greatly improve the performance and manufacturability of submillimeter-wave components.


Author(s):  
Feng Li ◽  
Andrew W. Owens ◽  
Qianyi Li

In recent years, the development of microbumps has allowed even smaller sizes of ICs to utilize the flip chip technique. In addition, microbumps have enabled the implementation of three-dimensional (3D) ICs, which drastically improve the spatial efficiency of packaging. However, as the bumps size decreases and the number increases, several process challenges must be considered, for example, the height consistency of bump, the ratio of miss and deformity bump and the yield and strength of interconnection, etc. Therefore, it is increasingly important to study the interconnection technology and materials of high-density microbump interconnection. After briefly introducing the common electronic packaging techniques, including wire bonding, tape-automated bonding and flip chip, this paper reviews microbumps as an advanced bonding technology. Techniques such as Controlled Collapse Chip Connection - New Process(C4NP), printing, insert bump bonding, and self-replication process are discussed and compared. C4NP can achieve low-cost, fine pitch bumping by utilizing varied lead-free solder alloys, which overcomes the limitation of existing bumping technologies. Depending on the microbump size, engraved mask stump, and photosensitive organic mask and squeegee are the two ways for micro-bump printing. The micro-insert bump bonding process is new to stack chips vertically, which has robust bonding structure and a simpler bonding process compared to Cu pillar bonding process. The self-replication process is using the surface tension property of molten solder between the micro bridged bump to get two bumps with same volume and geometries on each faced pairs of lands. The use of two common material for the microbump, Cu, Sn, and its alloys are presented along with the differences in the process for each. As with any technology, a new breakthrough addressing an issue brings with it its own set of shortfalls. Microbumps are no different. The various techniques and materials used to realize the reduced scale bonding method are subject to a number of challenges. Most prominent among them are electromigration, thermomigration, and thermallyinduced mechanical fatigue, which are discussed in this paper.


2012 ◽  
Vol 2012 (1) ◽  
pp. 000359-000365 ◽  
Author(s):  
MyoungSu Chae ◽  
Eric Ouyang ◽  
JaeHan Chung ◽  
DokOk Yu ◽  
SeonMo Gu ◽  
...  

The molded underfill (MUF) has become one of the trends in the IC packaging industry due to its simplification of assembly process steps and the saving of the cost. However, for the fine pitch flip chip bumping array, the void generation is one serious issue causing the short of the electrical connections and the cracking of the bumps. In this paper, the main focus is to predict the void generation and to compare with the experimental data. The early stage FEM numerical simulation not only can predict the risk of voids but also provide the best economic approach without the need to spend trial and error budget. A multiple segments substrate strip, with totally 64 packages populated on it, is used in the experiment. The manufacturing process parameters are programmed and recorded for comparison. The filling, packing, and curing of molding compound are carefully chosen in order to compare their effects. After the assembly process, each package is scanned with C-SAM inspection to check if the voids appear. For FEM numerical simulation, only one segment of the substrate strip, with totally 16 packages, is modeled to save computational resources and time. However, all the bumps, on each of the package, are modeled in order to check how the flow field is affected by the packages. In conclusion, we have obtained good match of experimental vs. simulation data. The prediction of voiding location is very close to each other.


2009 ◽  
Vol 4 (11) ◽  
pp. T11001-T11001
Author(s):  
E Skup ◽  
M Trimpl ◽  
R Yarema ◽  
J C Yun
Keyword(s):  

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