High Reliability Fine Pitch WLCSP for High Pin Count Applications

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001894-001907
Author(s):  
David Lawhead ◽  
Ronnie Yazzie ◽  
Tony Curtis ◽  
Guy Burgess ◽  
Ted Tessier
Keyword(s):  
Silver Content ◽  
High Reliability ◽  
Electrical Performance ◽  
Thermal Testing ◽  
Automotive Electronics ◽  
Wafer Level ◽  
Industry Standard ◽  
Fine Pitch ◽  
Board Level ◽  
Board Level Reliability

Wafer Level Chip Scale Packages (WLCSP) have seen wider adoption in hand held as well as automotive electronics in recent years due to their unmatched form factor reductions and improved electrical performance. WLCSP's have gained popularity in high pin count IC's with tighter pitches and increased reliability requirements. Enhanced board level reliability is achieved by using solder spheres with higher silver content. Traditionally, automotive applications require an improvement in thermal cycling over WLCPS found in hand held applications. This paper will study the differences in solder alloy and include a comparison to under filled parts to meet these reliability requirements. This study shows characteristic life that exceeds the industry standard requirements for the drop and thermal testing reliability testing.

Low Cost, High Reliability WLCSP for Higher Pin Counts

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002336-002359
Author(s):  
Tony Curtis ◽  
Senthil Sivaswamy ◽  
Ronnie Yazzie ◽  
David Lawhead ◽  
Theodore G. Tessier
Keyword(s):  
Test Performance ◽  
High Reliability ◽  
Low Cost ◽  
Cycling Performance ◽  
Wafer Level ◽  
End User ◽  
The Past ◽  
Board Level ◽  
Board Level Reliability ◽  
Proper Balance

The proliferation of Wafer Level Chip Scale Packages (WLCSPs) in portable handheld products has occurred due to the minimalist form factor, high reliability and low cost packaging that they afford. As the demand for WLCSPs has grown exponentially in recent years, the industry has also been coping concurrently with the technical challenges associated with increasing array sizes and more demanding end user reliability requirements. Since handsets are inherently prone to being dropped, they are particularly susceptible to this type of component failure though striking a proper balance of mechanical robustness and thermal cycling performance has remained an ongoing industry goal. Similar to other packages, WLCSPs have transitioned over the past decade from lead-based solder alloys to Lead Free (LF) solders. LF solder connections are especially susceptible to brittle fracture and can result in variations in drop test performance from one bump structure to the next. This paper will provide an overview of process and material add-on strategies that have been shown to considerably improve mechanical robustness for bump structures or bumping applications that are inherently less robust than others. Such supplemental improvements can result in passing Board Level Reliability qualification requirements which may otherwise be elusive or have limited levels of reliability reproducibility.

Package Qualification Envelope for 22FDX® Technology

2019 ◽  
Vol 2019 (1) ◽  
pp. 000169-000175
Author(s):  
Christian Klewer ◽  
Frank Kuechenmeister ◽  
Jens Paul ◽  
Dirk Breuer ◽  
Bjoern Boehme ◽  
...  
Keyword(s):  
Flip Chip ◽  
Silicon On Insulator ◽  
Wafer Level ◽  
Characterization Methods ◽  
Fully Depleted ◽  
Individual Market ◽  
The Individual ◽  
Key Aspects ◽  
Board Level ◽  
Board Level Reliability

Abstract This article describes the methodology used to derive the 22FDX® Fully-Depleted Silicon-On-Insulator (FDSOI) Chip Package Interaction (CPI) qualification envelope. In the first part it is discussed how the individual market segments influence the technology features and offerings, including BEOL stacks and package types. In the following, the criteria used for the selection of BEOL stacks, die and package sizes and the interconnect type for the qualification envelope are summarized and explained. The three CPI qualification stages and related characterization methods are presented. CPI test structures used in the envelope are reported and their placement on the technology qualification vehicles (TQV) is outlined on the basis of flip chip TQV. Finally, the paper presents the passing 22FDX® package and board level reliability results obtained for wire bond, flip chip, as well as wafer level fan-in and fan-out package technologies. Key aspects of the individual qualifications are reported.

High Reliability and High Performance 30μm Through-Package-Vias in Ultra-Thin Bare Glass Interposer

2014 ◽  
Vol 2014 (1) ◽  
pp. 000402-000408
Author(s):  
Venky Sundaram ◽  
Jialing Tong ◽  
Kaya Demir ◽  
Timothy Huang ◽  
Aric Shorey ◽  
...  
Keyword(s):  
High Performance ◽  
High Reliability ◽  
Low Cost ◽  
Electrical Performance ◽  
Mechanical Reliability ◽  
Bare Glass ◽  
Fine Pitch ◽  
Glass Panels ◽  
Accelerated Thermal Cycling ◽  
Frequency Behavior

This paper presents, for the first time, the thermo-mechanical reliability and the electrical performance of 30μm through package vias (TPVs) formed by Corning in ultra-thin low-cost bare glass interposers and metallized directly by sputter seed and electroplating. In contrast to glass interposers with polymer coated glass cores reported previously, this paper reports on direct metallization of thin and uncoated glass panels with fine pitch TPVs. The scalability of the unit processes to large panel sizes is expected to result in bare glass interposers at 2 to 10 times lower cost than silicon interposers fabricated using back end of line (BEOL) wafer processes. The thermo-mechanical reliability of 30μm TPVs was studied by conducting accelerated thermal cycling tests (TCT), with most via chains passing 1000 cycles from −55°C to 125°C. The high-frequency behavior of the TPVs was characterized by modeling, design and measurement up to 30 GHz.

Improvement of board level reliability for fine pitch PoP

2017 ◽  
Author(s):  
GyuWan Han ◽  
JinYoung Khim ◽  
KwangSeok Oh ◽  
WoonKab Jung ◽  
DongGun Lee ◽  
...  
Keyword(s):  
Fine Pitch ◽  
Board Level ◽  
Board Level Reliability
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