RF System in Packages (SiP) using Integrated Passive Devices

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001977-001995
Author(s):  
Kai Liu ◽  
YongTaek Lee ◽  
HyunTai Kim ◽  
Gwang Kim ◽  
Billy Ahn
Keyword(s):  
High Performance ◽  
Substrate Material ◽  
Electrical Performance ◽  
Low Loss ◽  
Passive Components ◽  
Cycle Times ◽  
Rf Power Amplifier ◽  
Small Form Factor ◽  
Rf Packaging ◽  
Tolerance Control

Passive components are indispensible parts used in System in Packages (SiP) for various functions, such as decoupling, biasing, resonating, filtering, matching, transforming, etc. Making passive components embedded inside laminate substrates is limited on passive density. SMD solutions are by far the most popular approaches in the industry, and may still be dominant for some times. As high integration and high performance have become a trend in the packaging solutions, integrated passive device (IPD) technology shows some unique features, which helps to achieve these goals, especially for RF packages. In the IPD process, low-loss substrate material is used, and therefore high-Q inductors can be built. In addition, thin-film IPD process has finer pitch feature and better tolerance control than other commonly available ones, such as PCB and LTCC technologies, which may yield very repeatable electrical performance, and provide packages of high integration. Several cases of study will be presented and here are some highlights of them. In case one, a most straightforward SiP approach is presented using QFN package, where several dies (including IPD dies) are implemented side-by-side. This approach may give fast developing cycle times. But importantly, wire-bonding models have big impact on performance from RF packaging, and should be obtained accurately for designs. Another case of study is a stack-die package, where inter-die coupling/cross talk could be a big issue as far as electrical performance is concerned. Placement of some critical parts, such as coils in IPD and in VCO, should be investigated very carefully in design phases. This leads to a concept of ‘IC/IPD/package’ co-design. Finally, a hybrid SiP package solution, where an IPD die is embedded in a mold compound along side with a RF power amplifier die, is presented. This approach (so called ‘eWLB’ packaging), results in the shortest interconnection between dies to dies and dies to balls. With the benefit from both the IPD process and the eWLB process (where low-loss mold materials are used), this approach may lead to high electrical performance and small form-factor at the same time.

Advanced Ceramic Structures and Materials for High-Reliability Millimeter-Wave Applications

2011 ◽  
Vol 2011 (CICMT) ◽  
pp. 000182-000185
Author(s):  
Iris Labadie
Keyword(s):  
Millimeter Wave ◽  
Semiconductor Device ◽  
High Reliability ◽  
Electrical Performance ◽  
Low Loss ◽  
Passive Components ◽  
Package Design ◽  
The Past ◽  
Performance Requirements ◽  
Circuit Components

Semiconductor device speeds and circuit operating frequencies have increased substantially over the past decade. Although millimeter-wave technology has been around for over 100 years, it is only within the past 5–10 years that increased demand for millimeter-wave commercial products and services has driven the development of new electronic package designs, low-loss materials, and the transformation of passive components to integrated and smaller geometries. High-reliability applications have employed millimeter-waves for several decades, but typically utilized heavy materials and distributed architectures. The transition of high-reliability millimeter-wave applications to new materials such as low-temperature co-fired ceramics requires innovative package designs to achieve comparable or better electrical performance in a much smaller form factor. Ceramic packaging technology continues to meet or exceed the performance requirements of high-reliability millimeter-wave applications with a broadened portfolio of material sets and innovative internal circuit components such as filter banks, antennas, and waveguides. Today's ceramic package design techniques and materials for applications within current and future high-reliability millimeter-wave markets will be discussed.

Passive Device Integration from Silicon Technology

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001967-001989
Author(s):  
Kai Liu ◽  
YongTaek Lee ◽  
HyunTai Kim ◽  
Gwang Kim ◽  
Guruprasad Badakere ◽  
...  
Keyword(s):  
Substrate Material ◽  
Electrical Performance ◽  
Band Pass Filter ◽  
Passive Components ◽  
Pass Filter ◽  
Passive Device ◽  
High Q ◽  
Silicon Technology ◽  
On Chip ◽  
The Right

Passive components are indispensible parts used in electronics circuits for various functions, such decoupling, biasing, resonating, filtering, matching, transforming, etc. These passive components can be made on chips, or in PCBs, or in SMDs. SOC (system-on-chip) solutions where all passives are implemented may be long-term goals, but suffer high cost and long development cycle times at the time being. Making passive components embedded inside laminate substrates is limited on passive density. SMD solutions are by far the most popular approaches in the industry, and may still be dominant for some times. Passive components consume 70%–80% area of an electric package in a SiP solution, and therefore it is a great deal to reduce the area of passive components, in order to reduce the size of entire package. We have developed an IPD (integrated passive device) process from silicon technology to make these passive components of high-Q performance, preferably to be used in RF packages. Low-loss substrate material is used in this process, and thick Cu layer is used for high-Q inductors. From this process, we can make capacitors in 330pF/mm sq density, and the Q-factor is around 30–35 peak for a 3nH–5 nH inductor. Most importantly, the thin-film IPD process has better tolerance control than other commonly available ones, such as PCB and LTCC technologies, which may results in very repeatable electrical performance, and provides packages in high integration. For a passive function block, using BPF (band-pass-filter) as an example, an IPD filter is typically two times smaller in X-Y size and half thinner in Z-height. This makes such IPD very suitable to be integrated in a SiP package. Using some case studies (individual IPD and chip-scale-module-package), we will present how high integration can be achieved, and where are the right spots to use IPD approaches other than SAW, or SMD, or LTCC solutions for RF SiP applications.

Mobile Device Passive Integration from Wafer Process

2011 ◽  
Vol 2011 (1) ◽  
pp. 000878-000886
Author(s):  
Kai Liu ◽  
YongTaek Lee ◽  
HyunTai Kim ◽  
MaPhooPwint Hlaing
Keyword(s):  
Signal Integrity ◽  
Form Factors ◽  
Electrical Performance ◽  
Passive Components ◽  
Small Form ◽  
Integration Schemes ◽  
Performance Functional ◽  
Functional Blocks ◽  
Small Form Factor ◽  
Significant Size

In this paper, we present some passive components made from silicon substrate technology (Integrated Passive Device process) and integration schemes using these components for RF applications. RF decoupling capacitors from this process are characterized on ESR and ESL performance. Functional blocks (filters, baluns, diplexers, matching, etc) made from the IPD process, have shown good electrical performance with small form-factor features. The thin profiles from the IPDs make them very suitable to be used inside laminate and QFN packages. System-in-Packages or multiple-chip-modules using IPD approaches may have significant size reduction. The low profiles and the small form-factors of the IPDs result in less cross-talk between the IPDs and their nearby components (chips, SMDs, and routing traces, etc), and therefore it is easier to maintain signal integrity for packages.

3D Integrated High-Precision Passives on Thin Glass Substrates for Miniaturized and High-Performance RF Components

2018 ◽  
Vol 15 (3) ◽  
pp. 107-116
Author(s):  
Zihan Wu ◽  
Junki Min ◽  
Markondeya Raj Pulugurtha ◽  
Siddharth Ravichandran ◽  
Venky Sundaram ◽  
...  
Keyword(s):  
High Precision ◽  
High Performance ◽  
Electrical Performance ◽  
Large Area ◽  
Low Loss ◽  
Thin Glass ◽  
Glass Substrates ◽  
Rf Components ◽  
Thin Polymer ◽  
The Impact

Abstract Double-side or 3-D integration of high-precision and high-performance bandpass and lowpass filters that are interconnected with through-vias were designed and demonstrated on 100-micron thin glass substrates for ultra-miniaturized diplexer components. A novel process for achieving high precision with large-area fabrication was developed to achieve much improved tolerance in electrical performance. High-precision, high quality factor, and high component densities with thin-film layers on glass were used to realize innovative topologies on glass for high out-of-band rejection and low insertion loss. Low-loss 100-μm thick glass cores and multiple layers of 15-μm thin polymer films were used to build the filters on substrates. The demonstrated diplexers have dimensions of 2.3 ×2.8 ×.2 mm. Aided by the dimensional stability of glass and process control with semiadditive patterning, the performance of the fabricated filters showed excellent correlation with the simulation. The impact of process-sensitivity analysis on diplexer performance was also analyzed. Finally, a unique and innovative process solution was demonstrated to control the process deviation and achieve good diplexer tolerance. The performance deviation was controlled by ~3.5X with the new process.

Flip-chip Packages with Periphery Cu Pillar Bumps as Wire Bond Replacement—Design, Modeling & Characterization

2013 ◽  
Vol 2013 (1) ◽  
pp. 000235-000235
Author(s):  
Zhe Li ◽  
Siow Chek Tan ◽  
Yee Huan Yew ◽  
Pheak Ti Teh ◽  
MJ Lee ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Electrical Performance ◽  
Package Design ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Field Programmable ◽  
Small Form Factor

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.

Microhardness Testing on Via Fill Material for Via In Pad Technology

2003 ◽  
Author(s):  
Norman J. Armendariz ◽  
Carolyn McCormick
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
Strong Dependence ◽  
Circuit Board ◽  
Electrical Performance ◽  
Gravimetric Analysis ◽  
Passive Components ◽  
Root Cause ◽  
Fill Material ◽  
Signal Routing

Abstract Via in pad PCB (Printed Circuit board) technology for passive components such as chip capacitors and resistors, provides the potential for improved signal routing density and reduced PCB area. Because of these improvements there is the potential for PCB cost reduction as well as gains in electrical performance through reduced impedance and inductance. However, not long after the implementation, double digit unit failures for solder joint electrical opens due to capacitor “tombstoning” began to occur. Failure modes included via fill material (solder mask) protrusion from the via as well as “out gassing” and related “tombstoning.” This failure analysis involved investigating a strong dependence on PCB supplier and, less obviously, manufacturing site. Other factors evaluated included via fill material, drill size, via fill thermal history and via fill amount or fill percent. The factor most implicated was incomplete cure of the via fill material. Previous thermal gravimetric analysis methods to determine level of polymerization or cure did not provide an ability to measure and demonstrate via fill cure level in small selected areas or its link to the failures. As a result, there was a metrology approach developed to establish this link and root-cause the failures in the field, which was based on microhardness techniques and noncontact via fill measuring metrologies.

scholarly journals Graphene Nanoribbon Gap Waveguides for Dispersionless and Low-Loss Propagation with Deep-Subwavelength Confinement

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1302
Author(s):  
Zhiyong Wu ◽  
Lei Zhang ◽  
Tingyin Ning ◽  
Hong Su ◽  
Irene Ling Li ◽  
...  
Keyword(s):  
High Performance ◽  
Chemical Potential ◽  
Shape Change ◽  
Optical Switch ◽  
Pulse Amplitude ◽  
Propagation Distance ◽  
Graphene Nanoribbon ◽  
Low Loss ◽  
High Loss ◽  
On Chip

Surface plasmon polaritons (SPPs) have been attracting considerable attention owing to their unique capabilities of manipulating light. However, the intractable dispersion and high loss are two major obstacles for attaining high-performance plasmonic devices. Here, a graphene nanoribbon gap waveguide (GNRGW) is proposed for guiding dispersionless gap SPPs (GSPPs) with deep-subwavelength confinement and low loss. An analytical model is developed to analyze the GSPPs, in which a reflection phase shift is employed to successfully deal with the influence caused by the boundaries of the graphene nanoribbon (GNR). It is demonstrated that a pulse with a 4 μm bandwidth and a 10 nm mode width can propagate in the linear passive system without waveform distortion, which is very robust against the shape change of the GNR. The decrease in the pulse amplitude is only 10% for a propagation distance of 1 μm. Furthermore, an array consisting of several GNRGWs is employed as a multichannel optical switch. When the separation is larger than 40 nm, each channel can be controlled independently by tuning the chemical potential of the corresponding GNR. The proposed GNRGW may raise great interest in studying dispersionless and low-loss nanophotonic devices, with potential applications in the distortionless transmission of nanoscale signals, electro-optic nanocircuits, and high-density on-chip communications.

scholarly journals Nanonet: Low-temperature-processed tellurium nanowire network for scalable p-type field-effect transistors and a highly sensitive phototransistor array

2021 ◽  
Vol 13 (1) ◽  
Author(s):  
Muhammad Naqi ◽  
Kyung Hwan Choi ◽  
Hocheon Yoo ◽  
Sudong Chae ◽  
Bum Jun Kim ◽  
...  
Keyword(s):  
Low Temperature ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Optical Measurements ◽  
Electrical Performance ◽  
Large Area ◽  
Nanowire Network ◽  
P Type ◽  
Nanowire Networks

AbstractLow-temperature-processed semiconductors are an emerging need for next-generation scalable electronics, and these semiconductors need to feature large-area fabrication, solution processability, high electrical performance, and wide spectral optical absorption properties. Although various strategies of low-temperature-processed n-type semiconductors have been achieved, the development of high-performance p-type semiconductors at low temperature is still limited. Here, we report a unique low-temperature-processed method to synthesize tellurium nanowire networks (Te-nanonets) over a scalable area for the fabrication of high-performance large-area p-type field-effect transistors (FETs) with uniform and stable electrical and optical properties. Maximum mobility of 4.7 cm2/Vs, an on/off current ratio of 1 × 104, and a maximum transconductance of 2.18 µS are achieved. To further demonstrate the applicability of the proposed semiconductor, the electrical performance of a Te-nanonet-based transistor array of 42 devices is also measured, revealing stable and uniform results. Finally, to broaden the applicability of p-type Te-nanonet-based FETs, optical measurements are demonstrated over a wide spectral range, revealing an exceptionally uniform optical performance.

scholarly journals Recent Advances in ZnO-Based Carbon Monoxide Sensors: Role of Doping

Sensors ◽  
2021 ◽  
Vol 21 (13) ◽  
pp. 4425
Author(s):  
Ana María Pineda-Reyes ◽  
María R. Herrera-Rivera ◽  
Hugo Rojas-Chávez ◽  
Heriberto Cruz-Martínez ◽  
Dora I. Medina
Keyword(s):  
Carbon Monoxide ◽  
High Performance ◽  
Gas Sensing ◽  
Experimental Studies ◽  
Electrical Performance ◽  
Long Term Stability ◽  
Sensing Applications ◽  
Recent Advances ◽  
Sensitivity And Selectivity ◽  
Doped Zno

Monitoring and detecting carbon monoxide (CO) are critical because this gas is toxic and harmful to the ecosystem. In this respect, designing high-performance gas sensors for CO detection is necessary. Zinc oxide-based materials are promising for use as CO sensors, owing to their good sensing response, electrical performance, cost-effectiveness, long-term stability, low power consumption, ease of manufacturing, chemical stability, and non-toxicity. Nevertheless, further progress in gas sensing requires improving the selectivity and sensitivity, and lowering the operating temperature. Recently, different strategies have been implemented to improve the sensitivity and selectivity of ZnO to CO, highlighting the doping of ZnO. Many studies concluded that doped ZnO demonstrates better sensing properties than those of undoped ZnO in detecting CO. Therefore, in this review, we analyze and discuss, in detail, the recent advances in doped ZnO for CO sensing applications. First, experimental studies on ZnO doped with transition metals, boron group elements, and alkaline earth metals as CO sensors are comprehensively reviewed. We then focused on analyzing theoretical and combined experimental–theoretical studies. Finally, we present the conclusions and some perspectives for future investigations in the context of advancements in CO sensing using doped ZnO, which include room-temperature gas sensing.

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