3D Passive Integrated Capacitors Towards Even Higher Integration

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001907-001930
Author(s):  
Sophie Gaborieau ◽  
Catherine Bunel ◽  
Franck Murray
Keyword(s):  
Development Program ◽  
High Density ◽  
Ceramic Technology ◽  
Advanced Technology ◽  
Fourth Generation ◽  
The Third ◽  
Low Profile ◽  
Metal Insulator Metal ◽  
High K Materials ◽  
Processing Techniques

IPDIA is involved in Silicon based 3D-IPD advanced technology. This very flexible technology is using standard processing techniques to integrate passive components such as inductors, resistors or capacitors into a silicon substrate. 3D high-density capacitor is at the forefront of IPDIA development program. First process generation with 25nF/mm2 and second generation reaching 80nF/mm2 have been in production for several years. The third generation with multiple metal-insulator-metal (MIM) layer stacks in the pores is reaching 250nF/mm2 and is being qualified now. Intrinsic low parasitic elements of these capacitors (low ESR and ESL) make it very attractive for DC decoupling and very competitive with the ceramic technology. Assembly can be performed using standard reflow soldering and its low profile also allows PICS capacitor integration in embedded module board technology. Sensors, healthcare and medical applications can benefit from this new development. To enable even higher integration, development activities are now focused on the third and fourth generation of high-density capacitors targeting ambitious 1μF/mm2. In this presentation, main characteristics of the PICS high-density capacitors will be described emphasizing on its capability, main applications and advantages versus discrete components. Then, in a second part, challenges raised by the increase of the capacitor density while keeping an acceptable breakdown voltage will be discussed. This includes the integration of high-k materials with adequate electrode and the research for maximizing the 3D silicon surface.

scholarly journals Fabrication of SmCoxNanoparticles as a Potential Candidate of Materials for Super-high-density Magnetic Memory: Use of Gold as the Third Element

2007 ◽  
Vol 36 (10) ◽  
pp. 1264-1265 ◽  
Author(s):  
Toru Matsushita ◽  
Junya Masuda ◽  
Takashi Iwamoto ◽  
Naoki Toshima
Keyword(s):  
High Density ◽  
Magnetic Memory ◽  
Potential Candidate ◽  
The Third

scholarly journals Maciej Ziemierski, Testamenty krakowskiej rodziny Królików z XVII w.

2020 ◽  
Vol 26 ◽  
pp. 11-41
Author(s):  
Maciej Ziemierski
Keyword(s):  
18Th Century ◽  
Family Members ◽  
17Th Century ◽  
16Th Century ◽  
Fourth Generation ◽  
Third Generation ◽  
The Third ◽  
The Family ◽  
The Town ◽  
Distinguished Member

17th century testaments of the Królik family from Krakow The article is dedicated to the Królik family from Krakow, who lived in the town from the late 16th century until the first years of the 18th century. The family members initially worked as tailors, later reinforcing the group of Krakow merchants in the third generation (Maciej Królik). Wojciech Królik – from the fourth generation – was a miner in Olkusz. The text omits the most distinguished member of the family, Wojciech’s oldest brother, the Krakow councillor Mikołaj Królik, whose figure has been covered in a separate work. The work shows the complicated religious relations in the family of non-Catholics, initially highly engaged in the life of the Krakow Congregation, but whose members gradually converted from Evangelism to Catholicism. As a result, Wojciech Królik and his siblings became Catholics. This work is complemented by four testaments of family members, with the first, Jakub Królik’s, being written in 1626 and the last one, Wojciech Królik’s, written in 1691.

Tuning the Mechanical Properties of High-Density Polyethylene by ECAE Process

2015 ◽  
Author(s):  
Catalin Fetecau ◽  
Felicia Stan ◽  
Laurentiu Sandu ◽  
Florin Susac
Keyword(s):  
Mechanical Properties ◽  
High Density Polyethylene ◽  
Equal Channel Angular Extrusion ◽  
Morphological Changes ◽  
Longitudinal Axis ◽  
High Density ◽  
Scanning Calorimetry ◽  
Plastic Deformations ◽  
The Third ◽  
Indentation Tests

This paper investigates the ability of the equal channel angular extrusion (ECAE) process to induce morphological changes and hence tune the mechanical properties of high-density polyethylene (HDPE). In this study, differential scanning calorimetry (DSC), compression and cylindrical macro-indentation tests have been used to investigate the evolution of the mechanical properties of HDPE processed by ECAE up to four passes via route BC, i.e. counter clockwise 90° billet rotation about its longitudinal axis. It was found that the ECAE process induces significant plastic deformations with changes in the crystalline structure. The ECAE process increased the HDPE crystallinity by 10 to 15%. The number of ECAE passes has a significant effect on the magnitude of the mechanical properties especially on the elastic modulus and yield stress. Young’s modulus and yield strength decreased with increasing the number of ECAE passes and reached a stationary state after the third pass.

A faster method for erosion and dilation of reservoir pore-complex images

1988 ◽  
Vol 25 (7) ◽  
pp. 1128-1131 ◽  
Author(s):  
J. R. Parker
Keyword(s):  
Flow Behavior ◽  
Reservoir Rock ◽  
Two Dimensional ◽  
Thin Sections ◽  
Reservoir Rocks ◽  
Image Processing Techniques ◽  
The Third ◽  
Computer Image Processing ◽  
Third Dimension ◽  
Processing Techniques

Studies of thin sections of reservoir rock have been conducted for some time with the goal of understanding flow behavior and estimating physical properties. These sections are essentially two dimensional, but it has always been assumed that the results obtained can be extrapolated to the third dimension. Computer image-processing techniques are often used in this sort of analysis because of the large amounts of data contained in a single digitized section image. One of the methods used to process these images is erosion–dilation, wherein layers of each pore are stripped off (erosion) and then replaced (dilation). This results in a smoothing of the pore perimeters and can be used to estimate pore radii, volume, and roughness. Because of the size of each image, erosion–dilation of images of the pore complex of reservoir rocks is a time-consuming process. A new method called global erosion is much faster, with no increase in memory requirement or decrease in accuracy. This should permit the processing of larger images or a greater number of small images than does the standard method.

Design, Simulation and Testing of High Density, High Current Micro-machined Embedded Capacitors

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000515-000534
Author(s):  
Aubrey Beal ◽  
C. Stevens ◽  
T. Baginski ◽  
M. Hamilton ◽  
R. Dean
Keyword(s):  
Integrated Circuits ◽  
Hafnium Oxide ◽  
Implementation Strategies ◽  
Atomic Layer ◽  
High Density ◽  
Embedded Capacitors ◽  
Passive Devices ◽  
Layer Deposition ◽  
High K ◽  
High K Materials

Due to increasing speed, density and number of signal paths in integrated circuits, motivations for high density capacitors capable of quickly sourcing large amounts of current have led to many design and fabrication investigations. This work outlines continued efforts to achieve devices which meet these stringent requirements and are compatible with standard silicon fabrication processes as well as silicon interposer technologies. Previous work has been further developed resulting in devices exhibiting greater capacitance values by employing geometries which maximize surface area. The Atomic Layer Deposition (ALD) of thin layered high K materials, such as Hafnium Oxide, as opposed to previous silicon-dioxide based devices effectively increased the capacitance per unit area of the structures. This paper outlines the design, fabrication, and testing of high density micro-machined embedded capacitors capable of quickly sourcing (i.e. risetimes greater than 100A/nsec) high currents (i.e. greater than 100A). These devices were successfully simulated then tested using a standard ringdown procedure. Generally, the resulting device characterization found during testing stages strongly correlates to the expected simulated device behavior. Subsequent descriptions and design challenges encountered during fabrication, testing and integration of these passive devices are outlined, as well as potential device integration and implementation strategies for use in silicon interposers. The modification and revision of several device generations is documented and presented. Increased device capacitive density, maximized current capabilities and minimized effects of series inductance and resistance are presented. These resulting thin, capacitive structures exhibit compatibility with Si interposer technology.

Design Considerations and Ring-down Characteristics of Micromachined, High Current Density Capacitors

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001380-001406
Author(s):  
Aubrey N. Beal ◽  
John Tatarchuk ◽  
Colin Stevens ◽  
Thomas Baginski ◽  
Michael Hamilton ◽  
...  
Keyword(s):  
Energy Storage ◽  
Surface Area ◽  
High Density ◽  
Energy Storage Devices ◽  
Capacitive Energy Storage ◽  
Passive Components ◽  
Storage Devices ◽  
Passive Devices ◽  
High K ◽  
High K Materials

The need for integrated passive components which meet the stringent power system requirements imposed by increased data rates, signal path density and challenging power distribution network topologies in integrated systems yield diverse motivations for high density, miniaturized capacitors capable of quickly sourcing large quantities of current. These diverse motivations have led to the realization of high density capacitor structures through the means of several technologies. These structures have been evaluated as high-speed, energy storage devices and their respective fabrication technologies have been closely compared for matching integrated circuit speed and density increase, chip current requirements, low resistance, low leakage current, high capacitance and compatibility with relatively high frequencies of operation (~1GHz). These technologies include devices that utilize pn junctions, Schottky barriers, optimized surface area techniques and the utilization of high dielectric constant (high-K) materials, such as hafnium oxide, as a dielectric layer through the means of atomic layer deposition (ALD). The resulting devices were micro-machined, large surface area, thin, high-density capacitor technologies optimized as embedded passive devices for thin silicon interposers. This work outlines the design, fabrication, simulation and testing of each device revision using standard silicon microfabrication processes and silicon interposer technologies. Consequently, capacitive storage devices were micro-machined with geometries which maximize surface area and exhibit the capability of sourcing 100A of current with a response time greater than 100 A/nsec through the use of thin layered, ALD high-K materials. The simulation and testing of these devices show general agreement when subjected to a standard ring-down procedure. This paper provides descriptions and design challenges encountered during fabrication, testing and integration of these passive devices. In addition, potential device integration and implementation strategies for use in silicon interposers are also provided. The modification and revision of several device generations is documented showing increased device capacitance density, maximized current capabilities and minimized effects of series inductance and resistance. The resulting structures are thin, capacitive devices that may be micro-machined using industry standard Si MEMS processes and are compatible with Si interposer 3D technologies. The subsequent design processes allow integrated passive components to be attached beneath chips in order to maximize system area and minimize the chip real estate required for capacitive energy storage devices.

Parylene as Thin Flexible 3-D Packaging Enabler for Biomedical Implants

2012 ◽  
Vol 2012 (1) ◽  
pp. 000176-000185
Author(s):  
Jimin Maeng ◽  
Dohyuk Ha ◽  
William J. Chappell ◽  
Pedro P. Irazoqui
Keyword(s):  
Transmission Lines ◽  
High Density ◽  
The Novel ◽  
Fully Integrated ◽  
Surface Mount ◽  
Passive Devices ◽  
Metal Insulator Metal ◽  
Small Form Factor ◽  
First Time ◽  
Sealing Layer

In this paper, the novel use of Parylene for implantable biomedical microsystems packaging is presented. Parylene is an excellent candidate material to be used for implantable and clinically usable miniature devices due to its biocompatibility, flexibility, near-hermeticity, and high-density integration capability in a small form factor. Here, we propose a novel all-Parylene packaging technique where Parylene is used as a package substrate, an isolation layer, a capacitor insulator, and a sealing layer. Fully-integrated embedded passive devices, transmission lines, and surface mount components on a thin-film multilayer Parylene substrate are described. Metal-insulator-metal capacitors are implemented on Parylene and their DC and RF properties are characterized. Further, high-density 3-D trench capacitors are developed on Parylene for the first time. By integrating embedded capacitors and antenna with surface mount diodes, a rectifier module is implemented. Wireless powering onto the Parylene package is demonstrated as a proof-of-concept for the implant package to be powered by external environment. The authors believe that the all-Parylene packaging method described here can be widely applied to other miniature implant applications.

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