Advances in 3D Memory and Logic Devices

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000502-000538 ◽  
Author(s):  
Robert Patti
Keyword(s):  
3D Integration ◽  
Logic Devices ◽  
3D Memory

Tezzaron is continuing to push the level of 3D integration. The latest results of a new 1-4Gb 3D DRAM will be presented along with the plans (and possibly some results) of further integration with other 3D host logic devices. Additionally, results from several other recent 3D integrations will be reviewed.

Utilizing Nanoprobing and Circuit Diagnostics to Identify Key Failure Mechanism of Otherwise Nonvisible Defects in 20 nm Logic Devices

2014 ◽  
Author(s):  
M.K. Dawood ◽  
C. Chen ◽  
P.K. Tan ◽  
S. James ◽  
P.S. Limin ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Contact Layer ◽  
Fault Isolation ◽  
Tem Analysis ◽  
Logic Devices ◽  
Technology Advancement ◽  
Transmission Electron ◽  
Voltage Contrast ◽  
Almost All ◽  
20 Nm

Abstract In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.

Fan-Out Wafer and Panel Level Packaging - A Platform for 3D Integration

2021 ◽  
Author(s):  
Tania Braun ◽  
Karl-Friedrich Becker ◽  
Michael Topper ◽  
Rolf Aschenbrenner ◽  
Martin Schneider-Ramelow
Keyword(s):  
3D Integration

scholarly journals Sidewall Slope Control of InP Via Holes for 3D Integration

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 89
Author(s):  
Jongwon Lee ◽  
Kilsun Roh ◽  
Sung-Kyu Lim ◽  
Youngsu Kim
Keyword(s):  
Inductively Coupled Plasma ◽  
Sio2 Layer ◽  
Etch Depth ◽  
Rf Power ◽  
3D Integration ◽  
Inductively Coupled ◽  
Wide Range ◽  
Via Holes ◽  
Dry Etch ◽  
Icp Etcher

This is the first demonstration of sidewall slope control of InP via holes with an etch depth of more than 10 μm for 3D integration. The process for the InP via holes utilizes a common SiO2 layer as an InP etch mask and conventional inductively coupled plasma (ICP) etcher operated at room temperature and simple gas mixtures of Cl2/Ar for InP dry etch. Sidewall slope of InP via holes is controlled within the range of 80 to 90 degrees by changing the ICP power in the ICP etcher and adopting a dry-etched SiO2 layer with a sidewall slope of 70 degrees. Furthermore, the sidewall slope control of the InP via holes in a wide range of 36 to 69 degrees is possible by changing the RF power in the etcher and introducing a wet-etched SiO2 layer with a small sidewall slope of 2 degrees; this wide slope control is due to the change of InP-to-SiO2 selectivity with RF power.

scholarly journals Liquid Metal‐Enabled Soft Logic Devices

2021 ◽  
pp. 2000246
Author(s):  
Dong-Dong Li ◽  
Tian-Ying Liu ◽  
Jiao Ye ◽  
Lei Sheng ◽  
Jing Liu
Keyword(s):  
Liquid Metal ◽  
Logic Devices ◽  
Soft Logic
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